Camera_driver: add Readme and example of captured image of FC

- add pulls up resistors to activation MOSFETs

.gitmodules

@@ -0,0 +1,3 @@
+[submodule "resources/Camera_driver/alohal"]
+	path = resources/Camera_driver/alohal
+	url = git@github.com:TheColonelYoung/ALOHAL.git

README.md

@@ -1,57 +1,42 @@
 # BUTCube
+Modules:
+- Solar panels (XY, Z) (not in stack)
+- EPS
+- Flight Computer
+- Mission computer
+- Communication
+- Sun sensor module (not in stack)
+- ? Attitude control
+- Access port module (not in stack)
 
-# Solar cells
-
-Digi-key filter: https://www.digikey.nl/products/en?FV=-5|23585
-
-Calculations for space are calculated with 1 mm space between panels
-In center of panel there should be attitude determination module with minimal size od 25mm x 25mm
-All calculation are only for one side of satelite
+# Solar panels
 
+## Solar cells
 #### SM141K04L
 - Link: https://www.digikey.nl/short/fvpwbf4h
-- Panel count: 10 (2S 5P)
-- Maximal power: 1.23 W
-- Voltage: 4.46 V
-- Dimensions: 29 x 23 mm (89 x 95 mm)
-- Weight: 3g (30g)
-- Configuration: 4 x 3 
-- Price (for 1 side): 28 € (750 CZK)
-
-#### KXOB25-05X3F
-- Link: https://www.digikey.nl/short/hdrrmtq3
-- Panel count: 32 (4S 8P)
+- Panel count: 8 (2S 4P)
 - Maximal power: 0.98 W
-- Voltage: 6.68 V
-- Dimensions: 23 x 8 mm (95 x 89 mm)
-- Weight: 0.5g (17g)
-- Configuration: 10 x 4
-- Price (for 1 side): 47 € (1229 CZK)
-- + Reflow solderable
-
-#### SM141K06LV
-- Link: https://www.digikey.nl/short/d80rrj7t
-- Panel count: 6 (2S 3P)
-- Maximal power: 1.10 W
-- Voltage: 6.7 V
-- Dimensions: 45 x 22 mm (91 x 91 mm)
-- Weight: 3g (18g)
-- Configuration: 2V 2H 2V
-- Price (for 1 side): 27 € (720 CZK)
+- Voltage: 4.46 V (MPPT)
+- Dimensions: 29 x 23 mm
+- Weight: 3g (24g)
+- Price (for 1 side): 28 € (750 CZK)
 
 #### SM141K04LV
 - Link: https://www.digikey.cz/short/r589mmbj
 - Panel count: 8 (2S 4P)
 - Maximal power: 0.98 W
-- Voltage: 5.52 V
-- Dimensions: 45 x 15 mm (81 x 95 mm)
+- Voltage: 4.46 V (MPPT)
+- Dimensions: 45 x 15 mm
 - Weight: 2.5g (20g)
-- Configuration: 2V 4H 2V
 - Price (for 1 side): 28 € (750 CZK)
 
 ## Solar module 
-- PCB with size cca 96x96 mm
-- In center of module is hole for another module (40x40 mm without corners)
+- Two sizes of solar panel PCBs
+    - Z - 100x100 mm with cutouts in corners for rails
+    - X,Y - 100x83
+- In center of module is hole for another module
+    - Approximate size of module is 46x30 mm
+    - Mounting to frame is via 4 bolts in corners of board
 - Integrated components: Optodiode, temperature measuring IC
 
 ## Sensors
@@ -59,15 +44,85 @@ All calculation are only for one side of satelite
 - Photo diode: 
     - VEMD5510C - 550nm (450-750)  - visible
     - VEMD5060X - 800nm (500-1000) - visible + IR
-    - VEMD5160X - 850nm (750-950)  - IR
+    - VEMD5160X - 850nm (750-950)  - IR (used)
 - ADC for photodiode: ADS7142
 
+# Cables
+- https://www.digikey.cz/product-detail/en/adafruit-industries-llc/3165/1528-1733-ND/6193585
+- https://www.digikey.cz/product-detail/en/adafruit-industries-llc/3167/1528-1735-ND/6193587
+- https://www.digikey.cz/product-detail/en/adafruit-industries-llc/3168/1528-1736-ND/6193588
+- https://www.digikey.cz/product-detail/en/adafruit-industries-llc/3164/1528-1732-ND/6193584
+
+- 30AWG resistance 0.3R per meter
+- Length in CubeSat cca 10-15 cm
+- Power loss in cables is 0.5mW in peek (0.05% per solar module)
+- Similar power loss will be at cable connectors
+
+# Stack connector
+- [https://cz.mouser.com/ProductDetail/200-SSQ12002TD]
+- 2x20 pins
+- Limits board to thickness of 1mm or less
+- Board spacing: 8.51 mm
+
+# EPS
+- Two identical modules on one board
+- Both connected to stack connector
+- Other board could be connected to both or one of then
+    - Power oring must be solved
+- Connected to main CAN
+
+## Power output
+- 3 regulated and monitored power rails - 1V8, 3V3, 5V
+    - Output regulator - TPS63002DRCR
+    - 0.8A (boost) up to 1.2A (buck) output
+    - 2.2 uH coil
+- 1 unregulated output of battery, monitored
+- Monitoring via current sensors (INA??)
+
+## Battery
+- Limit for CubeSat is 50Wh
+- Suggested battery has form factor 21700
+- One battery per EPS
+- Battery is mounted in battery holder
+    - Keystone 1122 - 1122
+    - Probably additional fixation is requested
+- Selected battery - https://www.conrad.cz/p/samsung-inr21700-50e-specialni-akumulator-21700-flat-top-li-ion-akumulator-36-v-4900-mah-2114678
+    - 3.6V, 4900mAh, 17.64Wh
+    - EPS module has around 35Wh (well in limit)
+
+## Battery heating
+- https://www.ges.cz/cz/odl-20r81-GES06914579.html
+- https://www.ges.cz/cz/odl-53r1-GES06914581.html
+- https://www.gme.cz/odporovy-drat-odp-kan02-3m
+- https://www.gme.cz/odporovy-drat-odp-kon03-3m
+
+- Heating should be designed for power around 1-4W
+- With 5.4R/m and battery input source (3.7V) length of wire for 2W heating should be around 1.2m (current 0.5A)
+    - 0.5A is probably to much, values around 0.2A are better -> 1W heating
+- For regulation could be used power switch with constant current regulation
+
+# Access port module
+Connectors:
+- USB-C
+    - data connected to mission computer or flight computer
+    - power connected to EPS for battery charging
+- 2x SWD port for programing and debugging of Flight and Mission computer
+- main CAN bus connector
+- UART debug port
+
+- Realized as stack of two PCB boards
+    - Front acts only as cover for connectors
+    - Connectors are mounted on rear board
+    - Connectors are accessible via cutouts in frontz board
+    - Rear board is mounted to front via column spacers
+
 # Other parts:
 - LTC4415 - Dual ideal diode with ORing
-- MAX16171
+- MAX16171 - Ideal Diode Controller with Reverse-Current Protection
 - BQ25798 - solar battery charger with dual-input selector and MPPT, I2C, https://www.ti.com/product/BQ25798
 - BAT54W-G - Low drop shottky diode, solar blocking diode
+- BQ27421YZFT-G1A - Fuel gauge
 
-
-
-
+# Digikey orders
+https://www.digikey.cz/short/8nmn4tr3
+https://www.digikey.cz/short/d4n94tbz

diagrams/Accesss_port_stackup.drawio

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diagrams/EPS.drawio

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modules/EPS/.gitignore

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+EPS-backups/
+EPS_V5/
+Hierarchy_test/
+Replicate_test/
+replicate_layout.log
+bom/
+gerbers/

modules/EPS/Activation_control.kicad_sch

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+
+  (uuid 11cd2ff5-feed-4db2-af14-43763d29bc27)
+
+  (paper "A4")
+
+  (title_block
+    (title "BUTCube - EPS")
+    (date "2021-06-01")
+    (rev "v1.0")
+    (company "VUT - FIT(STRaDe) & FME(IAE & IPE)")
+    (comment 1 "Author: Petr Malaník")
+  )
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+    (stroke (width 0.001) (type solid) (color 132 0 132 1))
+    (fill (color 72 72 72 1.0000))
+    (uuid 3e102a28-d5a4-4d2c-b73e-7fe3de18252f)
+    (property "Sheet name" "Activation logic" (id 0) (at 123.19 67.9441 0)
+      (effects (font (size 3 3) bold) (justify left bottom))
+    )
+    (property "Sheet file" "Activation_logic.kicad_sch" (id 1) (at 156.21 52.5789 0)
+      (effects (font (size 1.27 1.27)) (justify left top))
+    )
+    (pin "SW_#1" input (at 96.52 59.69 180)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid c2a33a28-dadb-442d-aa32-bbb4ece07e66)
+    )
+    (pin "SW_#2" input (at 96.52 64.77 180)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid 3417a9bb-88ca-4e87-9a36-9a73121a350a)
+    )
+    (pin "SW_#3" input (at 96.52 69.85 180)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid 1860ab65-10f5-4bba-b770-39f6b5f1c173)
+    )
+    (pin "SW_#4" input (at 96.52 74.93 180)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid 27cb6679-eaa4-4b9c-8f5c-060db5c86102)
+    )
+    (pin "SEP_EN" input (at 129.54 82.55 270)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid 5b7f14e9-fe77-4354-b099-1dfc14be7a18)
+    )
+    (pin "PWR_IN" input (at 96.52 80.01 180)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid dce503d9-c016-48af-bcbb-f98fde8cdc07)
+    )
+    (pin "RBF_PIN" input (at 96.52 54.61 180)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid 919b940f-c7ef-4489-923a-9cda92365379)
+    )
+    (pin "RBF_EN" input (at 163.83 82.55 270)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid da824daa-7f6d-4d11-ba31-0958504385a9)
+    )
+  )
+)

modules/EPS/Activation_switches.kicad_sch

@@ -0,0 +1,751 @@
+(kicad_sch (version 20210621) (generator eeschema)
+
+  (uuid 11cd2ff5-feed-4db2-af14-43763d29bc27)
+
+  (paper "A4")
+
+  (title_block
+    (title "BUTCube - EPS")
+    (date "2021-06-01")
+    (rev "v1.0")
+    (company "VUT - FIT(STRaDe) & FME(IAE & IPE)")
+    (comment 1 "Author: Petr Malaník")
+  )
+
+  (lib_symbols
+    (symbol "Connector_Generic_MountingPin:Conn_01x02_MountingPin" (pin_names (offset 1.016) hide) (in_bom yes) (on_board yes)
+      (property "Reference" "J" (id 0) (at 0 2.54 0)
+        (effects (font (size 1.27 1.27)))
+      )
+      (property "Value" "Conn_01x02_MountingPin" (id 1) (at 1.27 -5.08 0)
+        (effects (font (size 1.27 1.27)) (justify left))
+      )
+      (property "Footprint" "" (id 2) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "Datasheet" "~" (id 3) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_keywords" "connector" (id 4) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_description" "Generic connectable mounting pin connector, single row, 01x02, script generated (kicad-library-utils/schlib/autogen/connector/)" (id 5) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_fp_filters" "Connector*:*_1x??-1MP*" (id 6) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (symbol "Conn_01x02_MountingPin_1_1"
+        (text "Mounting" (at 0 -4.191 0)
+          (effects (font (size 0.381 0.381)))
+        )
+        (rectangle (start -1.27 -2.413) (end 0 -2.667)
+          (stroke (width 0.1524)) (fill (type none))
+        )
+        (rectangle (start -1.27 0.127) (end 0 -0.127)
+          (stroke (width 0.1524)) (fill (type none))
+        )
+        (rectangle (start -1.27 1.27) (end 1.27 -3.81)
+          (stroke (width 0.254)) (fill (type background))
+        )
+        (polyline
+          (pts
+            (xy -1.016 -4.572)
+            (xy 1.016 -4.572)
+          )
+          (stroke (width 0.1524)) (fill (type none))
+        )
+        (pin passive line (at -5.08 0 0) (length 3.81)
+          (name "Pin_1" (effects (font (size 1.27 1.27))))
+          (number "1" (effects (font (size 1.27 1.27))))
+        )
+        (pin passive line (at -5.08 -2.54 0) (length 3.81)
+          (name "Pin_2" (effects (font (size 1.27 1.27))))
+          (number "2" (effects (font (size 1.27 1.27))))
+        )
+        (pin passive line (at 0 -7.62 90) (length 3.048)
+          (name "MountPin" (effects (font (size 1.27 1.27))))
+          (number "MP" (effects (font (size 1.27 1.27))))
+        )
+      )
+    )
+    (symbol "Device:Jumper_NO_Small" (pin_numbers hide) (pin_names (offset 0.762) hide) (in_bom yes) (on_board yes)
+      (property "Reference" "JP" (id 0) (at 0 2.032 0)
+        (effects (font (size 1.27 1.27)))
+      )
+      (property "Value" "Jumper_NO_Small" (id 1) (at 0.254 -1.524 0)
+        (effects (font (size 1.27 1.27)))
+      )
+      (property "Footprint" "" (id 2) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "Datasheet" "~" (id 3) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_keywords" "jumper link bridge NO" (id 4) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_description" "Jumper, normally open, small symbol" (id 5) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_fp_filters" "SolderJumper*Open*" (id 6) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (symbol "Jumper_NO_Small_0_1"
+        (circle (center -1.016 0) (radius 0.508) (stroke (width 0)) (fill (type none)))
+        (circle (center 1.016 0) (radius 0.508) (stroke (width 0)) (fill (type none)))
+        (pin passive line (at -2.54 0 0) (length 1.016)
+          (name "1" (effects (font (size 1.27 1.27))))
+          (number "1" (effects (font (size 1.27 1.27))))
+        )
+        (pin passive line (at 2.54 0 180) (length 1.016)
+          (name "2" (effects (font (size 1.27 1.27))))
+          (number "2" (effects (font (size 1.27 1.27))))
+        )
+      )
+    )
+    (symbol "power:GND" (power) (pin_names (offset 0)) (in_bom yes) (on_board yes)
+      (property "Reference" "#PWR" (id 0) (at 0 -6.35 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "Value" "GND" (id 1) (at 0 -3.81 0)
+        (effects (font (size 1.27 1.27)))
+      )
+      (property "Footprint" "" (id 2) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "Datasheet" "" (id 3) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_keywords" "power-flag" (id 4) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_description" "Power symbol creates a global label with name \"GND\" , ground" (id 5) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (symbol "GND_0_1"
+        (polyline
+          (pts
+            (xy 0 0)
+            (xy 0 -1.27)
+            (xy 1.27 -1.27)
+            (xy 0 -2.54)
+            (xy -1.27 -1.27)
+            (xy 0 -1.27)
+          )
+          (stroke (width 0)) (fill (type none))
+        )
+      )
+      (symbol "GND_1_1"
+        (pin power_in line (at 0 0 270) (length 0) hide
+          (name "GND" (effects (font (size 1.27 1.27))))
+          (number "1" (effects (font (size 1.27 1.27))))
+        )
+      )
+    )
+  )
+
+  (junction (at 161.29 59.69) (diameter 0.9144) (color 0 0 0 0))
+  (junction (at 161.29 97.79) (diameter 0.9144) (color 0 0 0 0))
+  (junction (at 161.29 111.76) (diameter 1.016) (color 0 0 0 0))
+  (junction (at 161.29 125.73) (diameter 1.016) (color 0 0 0 0))
+  (junction (at 161.29 139.7) (diameter 1.016) (color 0 0 0 0))
+
+  (wire (pts (xy 149.86 59.69) (xy 161.29 59.69))
+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid 0617830d-9e9f-4e6a-8de2-e62c8a537546)
+  )
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+    (stroke (width 0) (type solid) (color 0 0 0 0))
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+  )
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+    (stroke (width 0) (type solid) (color 0 0 0 0))
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+  )
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+  )
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+    (stroke (width 0) (type solid) (color 0 0 0 0))
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+  )
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+    (stroke (width 0) (type solid) (color 0 0 0 0))
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+  )
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+  )
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+    (stroke (width 0) (type solid) (color 0 0 0 0))
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+  )
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+  )
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+  )
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+  )
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+  )
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+    (stroke (width 0) (type solid) (color 0 0 0 0))
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+  )
+  (wire (pts (xy 161.29 97.79) (xy 168.91 97.79))
+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid 05dcb2d3-b365-483e-8831-2445e97d4500)
+  )
+  (wire (pts (xy 161.29 104.14) (xy 161.29 105.41))
+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid 371099bd-a6e0-4326-b164-9a1e52471abe)
+  )
+  (wire (pts (xy 161.29 111.76) (xy 161.29 113.03))
+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid ef2afff7-ffe9-4e67-a72d-aab4ac40268a)
+  )
+  (wire (pts (xy 161.29 111.76) (xy 168.91 111.76))
+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid 8c3fc69c-1808-4bb9-aaf6-fb758f0e0ff9)
+  )
+  (wire (pts (xy 161.29 118.11) (xy 161.29 119.38))
+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid b655ff14-cbeb-41c5-8080-f2974e25740d)
+  )
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+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid 3782fc18-f55d-4d51-b4e9-cea9920bfcc3)
+  )
+  (wire (pts (xy 161.29 125.73) (xy 168.91 125.73))
+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid 1b6ed2a5-1586-4548-ad8e-137f4e9d3cf7)
+  )
+  (wire (pts (xy 161.29 132.08) (xy 161.29 133.35))
+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid 67595fff-7d50-4691-af4a-d83643843ee2)
+  )
+  (wire (pts (xy 161.29 139.7) (xy 161.29 140.97))
+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid d33d889a-e944-4b75-bb61-937c39cfed2a)
+  )
+  (wire (pts (xy 161.29 139.7) (xy 168.91 139.7))
+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid 727f7f9d-a9f4-4ad8-876c-81319e6dfeb9)
+  )
+  (wire (pts (xy 161.29 146.05) (xy 161.29 147.32))
+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid d4048748-501d-495c-bdbb-d669a1c6be59)
+  )
+
+  (text "As RBF pin is assume USB type-C connector. Female connector will be placed on access port.\nMale part of connector have soldered together pins VCC and GND.\nRBF_pin connector on EPS is connected to VCC and GND of female connector.\nWhen RBF USB male is inserted into access port switch is closed."
+    (at 125.73 36.83 0)
+    (effects (font (size 1.27 1.27)) (justify left bottom))
+    (uuid 229fa4a4-405f-4dd2-a20a-dc1a538e2063)
+  )
+  (text "If USB is used as RBF PIN then special care must be taken when connecting USB-RBF to RBF input of EPS.\nOn type-C VCC pin must be connected to output pin (1) of connector below.\nIf otherwise there is posibility that some dumb idiot will plug charger USB into this RBF USB connector.\nAs result of wrong connection 5V of USB is connected to GND of satellite system. And something will probably BURN!\n"
+    (at 125.73 49.53 0)
+    (effects (font (size 1.27 1.27)) (justify left bottom))
+    (uuid 5e35e0b0-8887-4a18-b8df-799bed7b5651)
+  )
+
+  (hierarchical_label "RBF_PIN" (shape input) (at 168.91 59.69 0)
+    (effects (font (size 1.27 1.27) (thickness 0.254)) (justify left))
+    (uuid 417d3438-4703-4b0d-85f9-32b85952a707)
+  )
+  (hierarchical_label "SW_#1" (shape input) (at 168.91 97.79 0)
+    (effects (font (size 1.27 1.27) (thickness 0.254)) (justify left))
+    (uuid bf6f84e7-5585-4b47-b471-765657dfedbd)
+  )
+  (hierarchical_label "SW_#2" (shape input) (at 168.91 111.76 0)
+    (effects (font (size 1.27 1.27) (thickness 0.254)) (justify left))
+    (uuid 1ae45ab4-1ac4-4c90-b6ed-1d12191b1810)
+  )
+  (hierarchical_label "SW_#3" (shape input) (at 168.91 125.73 0)
+    (effects (font (size 1.27 1.27) (thickness 0.254)) (justify left))
+    (uuid a206bd30-c5e1-485e-9e6d-c99d1128e213)
+  )
+  (hierarchical_label "SW_#4" (shape input) (at 168.91 139.7 0)
+    (effects (font (size 1.27 1.27) (thickness 0.254)) (justify left))
+    (uuid 00bdc853-14a6-4656-a005-b6ef1b7b21ae)
+  )
+
+  (symbol (lib_id "Device:Jumper_NO_Small") (at 161.29 63.5 90) (unit 1)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid 5103c2fe-be6a-4243-91e5-d95a4a167862)
+    (property "Reference" "JP7" (id 0) (at 162.4331 62.5915 90)
+      (effects (font (size 1.27 1.27)) (justify right))
+    )
+    (property "Value" "RBF_PIN" (id 1) (at 162.4331 65.3666 90)
+      (effects (font (size 1.27 1.27)) (justify right))
+    )
+    (property "Footprint" "Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical" (id 2) (at 161.29 63.5 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "~" (id 3) (at 161.29 63.5 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid cd41add1-4575-45f8-897e-aaeb36c22093))
+    (pin "2" (uuid e8869565-dd45-40fd-a1a5-a7672c31256e))
+  )
+
+  (symbol (lib_id "Device:Jumper_NO_Small") (at 161.29 101.6 90) (unit 1)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid 9995899c-d098-41ea-941d-2ced1e95659d)
+    (property "Reference" "JP8" (id 0) (at 162.4331 100.6915 90)
+      (effects (font (size 1.27 1.27)) (justify right))
+    )
+    (property "Value" "SW_#1" (id 1) (at 162.4331 103.4666 90)
+      (effects (font (size 1.27 1.27)) (justify right))
+    )
+    (property "Footprint" "Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical" (id 2) (at 161.29 101.6 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "~" (id 3) (at 161.29 101.6 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 5972d7ba-dd47-4bc0-bc0b-0f89570751d5))
+    (pin "2" (uuid 773fb101-9fcc-4554-9705-54bb805b51e1))
+  )
+
+  (symbol (lib_id "Device:Jumper_NO_Small") (at 161.29 115.57 90) (unit 1)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid 45ee22f5-6769-4d18-85de-6b6f9e805564)
+    (property "Reference" "JP9" (id 0) (at 162.4331 114.6615 90)
+      (effects (font (size 1.27 1.27)) (justify right))
+    )
+    (property "Value" "SW_#2" (id 1) (at 162.4331 117.4366 90)
+      (effects (font (size 1.27 1.27)) (justify right))
+    )
+    (property "Footprint" "Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical" (id 2) (at 161.29 115.57 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "~" (id 3) (at 161.29 115.57 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 50c4e20d-96ac-498c-b709-3afdf0f1cd51))
+    (pin "2" (uuid 045fb5b6-b711-4086-8e04-c7093964d0d5))
+  )
+
+  (symbol (lib_id "Device:Jumper_NO_Small") (at 161.29 129.54 90) (unit 1)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid 25264e05-2861-4b06-846c-3a0d6f16b226)
+    (property "Reference" "JP10" (id 0) (at 162.4331 128.6315 90)
+      (effects (font (size 1.27 1.27)) (justify right))
+    )
+    (property "Value" "SW_#3" (id 1) (at 162.4331 131.4066 90)
+      (effects (font (size 1.27 1.27)) (justify right))
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+)

modules/EPS/Battery_pack.kicad_sch

@@ -0,0 +1,928 @@
+(kicad_sch (version 20210621) (generator eeschema)
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+  (uuid 03566a80-89d5-403d-ab0b-feaa06c08259)
+
+  (paper "A4")
+
+  (title_block
+    (title "BUTCube - EPS")
+    (date "2021-06-01")
+    (rev "v1.0")
+    (company "VUT - FIT(STRaDe) & FME(IAE & IPE)")
+    (comment 1 "Author: Petr Malaník")
+  )
+
+  (lib_symbols
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+      )
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+        (effects (font (size 1.27 1.27)) hide)
+      )
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+        (effects (font (size 1.27 1.27)) hide)
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+)

modules/EPS/Battery_temp_control.kicad_sch

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+  (title_block
+    (title "BUTCube - EPS")
+    (date "2021-06-01")
+    (rev "v1.0")
+    (company "VUT - FIT(STRaDe) & FME(IAE & IPE)")
+    (comment 1 "Author: Petr Malaník")
+  )
+
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+    (stroke (width 0) (type dash) (color 0 0 0 0))
+    (uuid 4697bdd3-c590-4019-a2d9-cf1dbdc1472c)
+  )
+
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+    (effects (font (size 3 3)) (justify left bottom))
+    (uuid dd85f389-6929-421f-96f9-b0a37cc643fd)
+  )
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+    (effects (font (size 3 3)) (justify left bottom))
+    (uuid 61ead524-fec7-47b0-ac3d-82ab31054b0b)
+  )
+  (text "NTC voltage supply should be\ncontrolled by MCU to decrease\ncurrent soncumption during time\nwhen temperature is not measured"
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+    (effects (font (size 1.27 1.27)) (justify left bottom))
+    (uuid 997c3774-f962-4cdc-a009-88837a30bd5c)
+  )
+  (text "Assumed heater is resistive heating\n	wire fixed to battery with Kapton tape.\n\nHeating power should be in range of 1-4W.\n\nSuggested heating wire is Kanthal or Konstantan.\n\nWith nominal battery voltage of 3.7V,\n	resistance of wire for 2W heating\n	should be around 6.8R.\n\nFor uniform heat distribution there should be\n	more then at least 20 turns of wire or more."
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+    (effects (font (size 1.27 1.27)) (justify left bottom))
+    (uuid 461c1ad1-5390-4515-b8f6-2552d42852ec)
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+  (text "Heating can operate in two modes.\nConstant current and Pulse mode.\n\nSelection of right mode depends on heating power.\nPulse is better suited for high power heating.\n\nCurrent limiting resistor for load switch must be\n	adapted for each mode."
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modules/EPS/EPS.kicad_prl

@@ -0,0 +1,75 @@
+{
+  "board": {
+    "active_layer": 31,
+    "active_layer_preset": "",
+    "auto_track_width": false,
+    "hidden_nets": [],
+    "high_contrast_mode": 0,
+    "net_color_mode": 1,
+    "opacity": {
+      "pads": 1.0,
+      "tracks": 1.0,
+      "vias": 1.0,
+      "zones": 0.6
+    },
+    "ratsnest_display_mode": 0,
+    "selection_filter": {
+      "dimensions": true,
+      "footprints": true,
+      "graphics": true,
+      "keepouts": true,
+      "lockedItems": true,
+      "otherItems": true,
+      "pads": true,
+      "text": true,
+      "tracks": true,
+      "vias": true,
+      "zones": true
+    },
+    "visible_items": [
+      0,
+      1,
+      2,
+      3,
+      4,
+      5,
+      6,
+      8,
+      9,
+      10,
+      12,
+      13,
+      14,
+      15,
+      16,
+      17,
+      18,
+      19,
+      20,
+      21,
+      22,
+      23,
+      24,
+      25,
+      26,
+      27,
+      28,
+      29,
+      30,
+      32,
+      33,
+      34,
+      35,
+      36
+    ],
+    "visible_layers": "7fcffff_80000007",
+    "zone_display_mode": 0
+  },
+  "meta": {
+    "filename": "EPS.kicad_prl",
+    "version": 3
+  },
+  "project": {
+    "files": []
+  }
+}

modules/EPS/EPS.kicad_pro

@@ -0,0 +1,571 @@
+{
+  "board": {
+    "design_settings": {
+      "defaults": {
+        "board_outline_line_width": 0.09999999999999999,
+        "copper_line_width": 0.19999999999999998,
+        "copper_text_italic": false,
+        "copper_text_size_h": 1.5,
+        "copper_text_size_v": 1.5,
+        "copper_text_thickness": 0.3,
+        "copper_text_upright": false,
+        "courtyard_line_width": 0.049999999999999996,
+        "dimension_precision": 4,
+        "dimension_units": 3,
+        "dimensions": {
+          "arrow_length": 1270000,
+          "extension_offset": 500000,
+          "keep_text_aligned": true,
+          "suppress_zeroes": false,
+          "text_position": 0,
+          "units_format": 1
+        },
+        "fab_line_width": 0.09999999999999999,
+        "fab_text_italic": false,
+        "fab_text_size_h": 1.0,
+        "fab_text_size_v": 1.0,
+        "fab_text_thickness": 0.15,
+        "fab_text_upright": false,
+        "other_line_width": 0.15,
+        "other_text_italic": false,
+        "other_text_size_h": 1.0,
+        "other_text_size_v": 1.0,
+        "other_text_thickness": 0.15,
+        "other_text_upright": false,
+        "pads": {
+          "drill": 0.0,
+          "height": 0.43,
+          "width": 0.37
+        },
+        "silk_line_width": 0.15,
+        "silk_text_italic": false,
+        "silk_text_size_h": 1.0,
+        "silk_text_size_v": 1.0,
+        "silk_text_thickness": 0.15,
+        "silk_text_upright": false,
+        "zones": {
+          "45_degree_only": false,
+          "min_clearance": 0.19999999999999998
+        }
+      },
+      "diff_pair_dimensions": [
+        {
+          "gap": 0.0,
+          "via_gap": 0.0,
+          "width": 0.0
+        }
+      ],
+      "drc_exclusions": [],
+      "meta": {
+        "version": 2
+      },
+      "rule_severities": {
+        "annular_width": "error",
+        "clearance": "error",
+        "copper_edge_clearance": "error",
+        "courtyards_overlap": "error",
+        "diff_pair_gap_out_of_range": "error",
+        "diff_pair_uncoupled_length_too_long": "error",
+        "drill_out_of_range": "error",
+        "duplicate_footprints": "warning",
+        "extra_footprint": "warning",
+        "hole_clearance": "error",
+        "hole_near_hole": "error",
+        "invalid_outline": "error",
+        "item_on_disabled_layer": "error",
+        "items_not_allowed": "error",
+        "length_out_of_range": "error",
+        "malformed_courtyard": "error",
+        "microvia_drill_out_of_range": "error",
+        "missing_courtyard": "ignore",
+        "missing_footprint": "warning",
+        "net_conflict": "warning",
+        "npth_inside_courtyard": "ignore",
+        "padstack": "error",
+        "pth_inside_courtyard": "ignore",
+        "shorting_items": "error",
+        "silk_over_copper": "error",
+        "silk_overlap": "error",
+        "skew_out_of_range": "error",
+        "too_many_vias": "error",
+        "track_dangling": "warning",
+        "track_width": "error",
+        "tracks_crossing": "error",
+        "unconnected_items": "error",
+        "unresolved_variable": "error",
+        "via_dangling": "warning",
+        "zone_has_empty_net": "error",
+        "zones_intersect": "error"
+      },
+      "rules": {
+        "allow_blind_buried_vias": false,
+        "allow_microvias": false,
+        "max_error": 0.005,
+        "min_clearance": 0.15,
+        "min_copper_edge_clearance": 0.0,
+        "min_hole_clearance": 0.0,
+        "min_hole_to_hole": 0.3,
+        "min_microvia_diameter": 0.19999999999999998,
+        "min_microvia_drill": 0.09999999999999999,
+        "min_silk_clearance": 0.0,
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modules/EPS/EPS_unit.kicad_sch

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+    (date "2021-06-01")
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+      (uuid 72f80d07-077a-4a93-9b22-31420ad2a1dc)
+    )
+    (pin "I2C_SCL" input (at 125.73 83.82 180)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid 9e0ae108-7b37-478c-8dec-4f6c00ecb3c9)
+    )
+    (pin "I2C_SDA" input (at 125.73 80.01 180)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid 2e965014-1c2e-45ab-a6e5-a6238e33a7d4)
+    )
+    (pin "BAT_ALERT" input (at 125.73 92.71 180)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid ff1d929a-3a8b-4bed-a7ba-96c06d840db6)
+    )
+    (pin "BAT_IRQ" input (at 125.73 88.9 180)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid de56b76e-094f-4107-bc5b-47ee33872851)
+    )
+    (pin "HEAT_EN" input (at 125.73 132.08 180)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid 4121d607-c11d-4c46-8a0f-925b52fe0003)
+    )
+    (pin "HEAT_FAULT" input (at 125.73 135.89 180)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid ca194ea8-1edd-4322-b941-c3a0ec21fd2a)
+    )
+    (pin "OUT_CUR" input (at 193.04 83.82 0)
+      (effects (font (size 1.27 1.27)) (justify right))
+      (uuid 71f36ff7-5afd-42a1-abaa-53a998af7f18)
+    )
+    (pin "MCU_POWER" input (at 193.04 125.73 0)
+      (effects (font (size 1.27 1.27)) (justify right))
+      (uuid 655ebdfd-6020-4d72-96f4-f53c8947fe23)
+    )
+    (pin "ADC_CS" input (at 193.04 140.97 0)
+      (effects (font (size 1.27 1.27)) (justify right))
+      (uuid 11d20086-7696-4ff4-b6d1-cd3f29e229a8)
+    )
+    (pin "SPI_SCK" input (at 193.04 137.16 0)
+      (effects (font (size 1.27 1.27)) (justify right))
+      (uuid 30c674ee-e46b-4f7d-a717-e203df9bb8ba)
+    )
+    (pin "SPI_MISO" input (at 193.04 129.54 0)
+      (effects (font (size 1.27 1.27)) (justify right))
+      (uuid c58a7519-2d64-4265-a558-80e9e9728464)
+    )
+    (pin "SPI_MOSI" input (at 193.04 133.35 0)
+      (effects (font (size 1.27 1.27)) (justify right))
+      (uuid 95fe481f-c7dc-4741-b116-e117eafdde43)
+    )
+    (pin "NTC_REF" input (at 125.73 140.97 180)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid c2b61890-eec5-4774-8645-4351768df160)
+    )
+    (pin "ADC_CONV_EN" input (at 193.04 144.78 0)
+      (effects (font (size 1.27 1.27)) (justify right))
+      (uuid 64bd5426-66ca-40db-a5db-6eeca1cc65f8)
+    )
+  )
+
+  (sheet (at 151.13 48.26) (size 24.13 16.51)
+    (stroke (width 0.001) (type solid) (color 132 0 132 1))
+    (fill (color 72 72 72 1.0000))
+    (uuid d47b1e7e-fcc0-4d86-b637-7d4c2188f2da)
+    (property "Sheet name" "Output control" (id 0) (at 152.4 52.7041 0)
+      (effects (font (size 2 2)) (justify left bottom))
+    )
+    (property "Sheet file" "Output_control.kicad_sch" (id 1) (at 151.13 44.9589 0)
+      (effects (font (size 1.27 1.27)) (justify left top))
+    )
+    (pin "PWR_IN" input (at 151.13 57.15 180)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid 407b2c46-2f38-4907-bd9e-75c2f5abedbc)
+    )
+    (pin "PWR_OUT" input (at 175.26 57.15 0)
+      (effects (font (size 1.27 1.27)) (justify right))
+      (uuid 1fd87d4f-bff2-405f-a5d8-aabb3630041a)
+    )
+    (pin "I_SEN" input (at 162.56 64.77 270)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid 05f17fba-d3e9-4370-bbfc-51f11cec8721)
+    )
+  )
+
+  (sheet (at 193.04 48.26) (size 50.8 16.51)
+    (stroke (width 0.001) (type solid) (color 132 0 132 1))
+    (fill (color 72 72 72 1.0000))
+    (uuid e90aa45b-e371-4d9f-a40f-45b62d6b0cc2)
+    (property "Sheet name" "Power supplies" (id 0) (at 209.55 52.7041 0)
+      (effects (font (size 2 2)) (justify left bottom))
+    )
+    (property "Sheet file" "Power_supplies.kicad_sch" (id 1) (at 193.04 44.9589 0)
+      (effects (font (size 1.27 1.27)) (justify left top))
+    )
+    (pin "PWR_IN" input (at 193.04 57.15 180)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid d6671ecf-d3af-4485-979f-0806e2f81155)
+    )
+    (pin "5V" input (at 243.84 62.23 0)
+      (effects (font (size 1.27 1.27)) (justify right))
+      (uuid e68527f4-c1aa-423e-8273-8d92364d7b88)
+    )
+    (pin "VBAT" input (at 243.84 50.8 0)
+      (effects (font (size 1.27 1.27)) (justify right))
+      (uuid 513ef331-0f4e-4e7d-b342-194b162082c3)
+    )
+    (pin "1V8" input (at 243.84 54.61 0)
+      (effects (font (size 1.27 1.27)) (justify right))
+      (uuid 4fcf45a2-45c3-444c-bd0d-75470eb4cd06)
+    )
+    (pin "3V3" input (at 243.84 58.42 0)
+      (effects (font (size 1.27 1.27)) (justify right))
+      (uuid 1c5dd96f-99ad-4538-b029-2051b15e8452)
+    )
+    (pin "3V3_CUR" input (at 231.14 64.77 270)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid bbbae466-e1b8-4adf-a142-f742cac40c52)
+    )
+    (pin "5V_CUR" input (at 234.95 64.77 270)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid 3630eed7-1388-420d-8275-4e930e27af0b)
+    )
+    (pin "VBAT_CUR" input (at 223.52 64.77 270)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid 592a4f43-905f-4ca2-8cfc-ea35498cee48)
+    )
+    (pin "1V8_CUR" input (at 227.33 64.77 270)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid 36316930-67e2-4eeb-8ac3-790981021935)
+    )
+    (pin "3V3_EN" input (at 215.9 64.77 270)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid 34a98c1a-cddd-4f5d-96b6-cf679b5bc40f)
+    )
+    (pin "MCU_POWER" input (at 204.47 64.77 270)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid 67e68db4-8eb2-4948-816e-ba9d9694898d)
+    )
+    (pin "VBAT_EN" input (at 208.28 64.77 270)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid ef0180fb-e2df-42f3-908f-45620bc6b2e7)
+    )
+    (pin "1V8_EN" input (at 212.09 64.77 270)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid 71f8be9b-a42b-43f3-84d3-0b810558d90c)
+    )
+    (pin "5V_EN" input (at 219.71 64.77 270)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid be96fd94-f4b6-4244-9758-e8b8404cb727)
+    )
+  )
+
+  (sheet (at 26.67 62.23) (size 24.13 15.24)
+    (stroke (width 0.001) (type solid) (color 132 0 132 1))
+    (fill (color 72 72 72 1.0000))
+    (uuid d0e7f43c-19e1-457f-9b3c-08ae18c73b14)
+    (property "Sheet name" "Solar input" (id 0) (at 30.48 66.6741 0)
+      (effects (font (size 2 2)) (justify left bottom))
+    )
+    (property "Sheet file" "Solar_input.kicad_sch" (id 1) (at 26.67 77.9789 0)
+      (effects (font (size 1.27 1.27)) (justify left top))
+    )
+    (pin "SOLAR_OUT" input (at 50.8 69.85 0)
+      (effects (font (size 1.27 1.27)) (justify right))
+      (uuid 6ac7e326-432e-4bf0-a7f5-7375f0235184)
+    )
+  )
+)

modules/EPS/Power_supplies.kicad_sch

@@ -0,0 +1,314 @@
+(kicad_sch (version 20210621) (generator eeschema)
+
+  (uuid 11cd2ff5-feed-4db2-af14-43763d29bc27)
+
+  (paper "A4")
+
+  (title_block
+    (title "BUTCube - EPS")
+    (date "2021-06-01")
+    (rev "v1.0")
+    (company "VUT - FIT(STRaDe) & FME(IAE & IPE)")
+    (comment 1 "Author: Petr Malaník")
+  )
+
+  (lib_symbols
+  )
+
+  (junction (at 99.06 72.39) (diameter 1.016) (color 0 0 0 0))
+  (junction (at 99.06 90.17) (diameter 1.016) (color 0 0 0 0))
+  (junction (at 99.06 110.49) (diameter 0.9144) (color 0 0 0 0))
+
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+  (no_connect (at 146.05 160.02) (uuid 0f9b5c1b-dfd7-4056-955d-8845a7692d7a))
+
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+  )
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+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid 0d305a69-f99f-4ec6-a468-a56badcbc1b4)
+  )
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+    (stroke (width 0) (type solid) (color 0 0 0 0))
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+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid 0d305a69-f99f-4ec6-a468-a56badcbc1b4)
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+    (stroke (width 0) (type solid) (color 0 0 0 0))
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+    (stroke (width 0) (type solid) (color 0 0 0 0))
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+  )
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+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid 9d2af3ab-027d-4d1d-a7d9-57564eba0330)
+  )
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+    (stroke (width 0) (type solid) (color 0 0 0 0))
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+    (stroke (width 0) (type solid) (color 0 0 0 0))
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+    (uuid 83a39ed9-6718-4347-800c-b744fa37bee9)
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+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid 53995eb9-2453-4387-b19a-7e38fc775b24)
+  )
+  (wire (pts (xy 146.05 69.85) (xy 157.48 69.85))
+    (stroke (width 0) (type solid) (color 0 0 0 0))
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+  )
+  (wire (pts (xy 146.05 76.2) (xy 157.48 76.2))
+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid d0e33247-25ed-4687-ab86-fe8a82e08962)
+  )
+  (wire (pts (xy 146.05 107.95) (xy 157.48 107.95))
+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid 0c0b0972-a13c-4ce5-8f0d-bf5b61b93747)
+  )
+  (wire (pts (xy 146.05 114.3) (xy 157.48 114.3))
+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid fa1f9fdf-81f7-4bdc-a147-cde6db202784)
+  )
+  (wire (pts (xy 146.05 120.65) (xy 157.48 120.65))
+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid a89e68ff-df7b-4c66-9a84-b3cddbe6a2ab)
+  )
+  (wire (pts (xy 146.05 146.05) (xy 157.48 146.05))
+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid b70e8a35-cff6-4734-884c-e411dcf5d5bf)
+  )
+  (wire (pts (xy 146.05 153.67) (xy 157.48 153.67))
+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid 722b2a3c-24b1-4314-bc49-0c64c836db19)
+  )
+
+  (text "Power capabilities" (at 185.42 29.21 0)
+    (effects (font (size 2 2) (thickness 0.4) bold) (justify left bottom))
+    (uuid 29e65b12-d5b3-409b-b01d-336510e760b4)
+  )
+  (text "VBAT voltage range: 2.8-4.2V\nVBAT maximal current: 4A\n\n1.8V rail maximal current: 0.8A\n3.3V rail maximal current:\n	VBAT bellow 3.3V (boost) - 0.8A\n     VBAT above 3.3V (buck)  - 1.2A\n5.0V rail maximal current: 1.2A\n\nMaximal shared current draw from battery: 5A\n"
+    (at 185.42 50.8 0)
+    (effects (font (size 1.27 1.27)) (justify left bottom))
+    (uuid 333eb2cb-d65b-4e6a-845b-efb1efbc71c0)
+  )
+  (text "Each power supply has current monitoring stage.\nEach rail could be disabled by supervisor MCU.\nPower for supervisor MCU is handled by 3.3V power supply.\n"
+    (at 185.42 80.01 0)
+    (effects (font (size 1.27 1.27)) (justify left bottom))
+    (uuid b8b0e794-d0fa-46a0-82e4-45da8cc0114a)
+  )
+  (text "Supervisor is powered even if 3.3V rail\n	is disabled (PER_POWER - MCU_POWER).\nSo when supervisor disable 3.3V rail,\n	his own power is still working.\nSupervisor has own separate power protection."
+    (at 185.42 116.84 0)
+    (effects (font (size 1.27 1.27)) (justify left bottom))
+    (uuid 85dee85c-90cd-477d-89b9-25f580488a67)
+  )
+
+  (hierarchical_label "PWR_IN" (shape input) (at 91.44 90.17 180)
+    (effects (font (size 1.27 1.27) (thickness 0.254)) (justify right))
+    (uuid 80b20b19-e50a-4c7b-aaa8-f7a2a3696371)
+  )
+  (hierarchical_label "VBAT_EN" (shape input) (at 109.22 43.18 180)
+    (effects (font (size 1.27 1.27) (thickness 0.254)) (justify right))
+    (uuid 166c9974-8568-461e-8496-e87b6746a1d4)
+  )
+  (hierarchical_label "1V8_EN" (shape input) (at 109.22 80.01 180)
+    (effects (font (size 1.27 1.27) (thickness 0.254)) (justify right))
+    (uuid 7fae7624-9804-43b9-bcb7-d8430c2ccf88)
+  )
+  (hierarchical_label "3V3_EN" (shape input) (at 109.22 118.11 180)
+    (effects (font (size 1.27 1.27) (thickness 0.254)) (justify right))
+    (uuid 47e2ef63-aeaa-492f-a61d-47a68268009f)
+  )
+  (hierarchical_label "5V_EN" (shape input) (at 109.22 156.21 180)
+    (effects (font (size 1.27 1.27) (thickness 0.254)) (justify right))
+    (uuid 2c580ef3-28f8-4a4d-b39d-3d68c299a884)
+  )
+  (hierarchical_label "VBAT_CUR" (shape input) (at 157.48 34.29 0)
+    (effects (font (size 1.27 1.27) (thickness 0.254)) (justify left))
+    (uuid f766495d-da71-4322-afc7-97a556887217)
+  )
+  (hierarchical_label "VBAT" (shape input) (at 157.48 43.18 0)
+    (effects (font (size 1.27 1.27) (thickness 0.254)) (justify left))
+    (uuid d5ad2c01-6bc9-4744-a2bb-d56299c54c32)
+  )
+  (hierarchical_label "1V8_CUR" (shape input) (at 157.48 69.85 0)
+    (effects (font (size 1.27 1.27) (thickness 0.254)) (justify left))
+    (uuid 5e429f1e-0e54-4e40-9937-f75b16d09b25)
+  )
+  (hierarchical_label "1V8" (shape input) (at 157.48 76.2 0)
+    (effects (font (size 1.27 1.27) (thickness 0.254)) (justify left))
+    (uuid 04e713db-464f-4bbc-863c-65ac6232b8a1)
+  )
+  (hierarchical_label "3V3_CUR" (shape input) (at 157.48 107.95 0)
+    (effects (font (size 1.27 1.27) (thickness 0.254)) (justify left))
+    (uuid db387590-046b-4611-a634-2619eab5ecd9)
+  )
+  (hierarchical_label "3V3" (shape input) (at 157.48 114.3 0)
+    (effects (font (size 1.27 1.27) (thickness 0.254)) (justify left))
+    (uuid 20168af5-be22-43b9-a37e-8175fde5082e)
+  )
+  (hierarchical_label "MCU_POWER" (shape input) (at 157.48 120.65 0)
+    (effects (font (size 1.27 1.27) (thickness 0.254)) (justify left))
+    (uuid e7f4b67d-d22e-433e-a21b-20135d847a2f)
+  )
+  (hierarchical_label "5V_CUR" (shape input) (at 157.48 146.05 0)
+    (effects (font (size 1.27 1.27) (thickness 0.254)) (justify left))
+    (uuid 79ae5be6-e95c-446a-bc46-fa8c36490b30)
+  )
+  (hierarchical_label "5V" (shape input) (at 157.48 153.67 0)
+    (effects (font (size 1.27 1.27) (thickness 0.254)) (justify left))
+    (uuid fe43b749-8a0a-4eb8-b44f-3137985cebb9)
+  )
+
+  (sheet (at 113.03 27.94) (size 33.02 20.32) (fields_autoplaced)
+    (stroke (width 0.001) (type solid) (color 132 0 132 1))
+    (fill (color 72 72 72 1.0000))
+    (uuid 4813e8c7-3f5a-4c5f-98f0-ec2a381e611e)
+    (property "Sheet name" "Power_VBAT" (id 0) (at 113.03 27.3043 0)
+      (effects (font (size 1.27 1.27)) (justify left bottom))
+    )
+    (property "Sheet file" "Power_VBAT.kicad_sch" (id 1) (at 113.03 48.7687 0)
+      (effects (font (size 1.27 1.27)) (justify left top))
+    )
+    (pin "OUT" input (at 146.05 43.18 0)
+      (effects (font (size 1.27 1.27)) (justify right))
+      (uuid 9604957f-2e31-4dee-a6e0-56d226159764)
+    )
+    (pin "IN" input (at 113.03 34.29 180)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid b1586977-7613-4a43-bbb2-d708f72f04a9)
+    )
+    (pin "I_SEN" input (at 146.05 34.29 0)
+      (effects (font (size 1.27 1.27)) (justify right))
+      (uuid fdebc402-3b08-4689-9033-fc25aaaea6a4)
+    )
+    (pin "EN" input (at 113.03 43.18 180)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid 7cf2323d-26b5-4e60-b6b6-98444a051f03)
+    )
+  )
+
+  (sheet (at 113.03 66.04) (size 33.02 20.32) (fields_autoplaced)
+    (stroke (width 0.001) (type solid) (color 132 0 132 1))
+    (fill (color 72 72 72 1.0000))
+    (uuid a12e4ae2-0082-44ab-871d-8bf2750427af)
+    (property "Sheet name" "Power_supply_1V8" (id 0) (at 113.03 65.4043 0)
+      (effects (font (size 1.27 1.27)) (justify left bottom))
+    )
+    (property "Sheet file" "Power_supply.kicad_sch" (id 1) (at 113.03 86.8687 0)
+      (effects (font (size 1.27 1.27)) (justify left top))
+    )
+    (pin "IN" input (at 113.03 72.39 180)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid 57a5de67-c708-4b8c-ba3e-83262b271ac9)
+    )
+    (pin "OUT" input (at 146.05 76.2 0)
+      (effects (font (size 1.27 1.27)) (justify right))
+      (uuid 749f5877-5af6-4806-bbee-89a44518c5e8)
+    )
+    (pin "I_SEN" input (at 146.05 69.85 0)
+      (effects (font (size 1.27 1.27)) (justify right))
+      (uuid c0eaf814-d292-4d0b-9f69-397ce7fe1b5c)
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+    (pin "EN" input (at 113.03 80.01 180)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid 8dd9a299-bfff-4f8b-a280-54b9874e18fe)
+    )
+    (pin "PER_POWER" input (at 146.05 82.55 0)
+      (effects (font (size 1.27 1.27)) (justify right))
+      (uuid c7f6ad5a-4e85-43f9-9799-f1f536851a5f)
+    )
+  )
+
+  (sheet (at 113.03 104.14) (size 33.02 20.32) (fields_autoplaced)
+    (stroke (width 0.001) (type solid) (color 132 0 132 1))
+    (fill (color 72 72 72 1.0000))
+    (uuid b028d684-e73b-4aba-a10d-751a54ede8f8)
+    (property "Sheet name" "Power_supply_3V3" (id 0) (at 113.03 103.5043 0)
+      (effects (font (size 1.27 1.27)) (justify left bottom))
+    )
+    (property "Sheet file" "Power_supply.kicad_sch" (id 1) (at 113.03 124.9687 0)
+      (effects (font (size 1.27 1.27)) (justify left top))
+    )
+    (pin "IN" input (at 113.03 110.49 180)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid 3f0b5de9-2dc8-4ace-9a16-fbf7fb7b4c14)
+    )
+    (pin "OUT" input (at 146.05 114.3 0)
+      (effects (font (size 1.27 1.27)) (justify right))
+      (uuid df5d903e-34ae-4627-ae72-4906bda94d2c)
+    )
+    (pin "I_SEN" input (at 146.05 107.95 0)
+      (effects (font (size 1.27 1.27)) (justify right))
+      (uuid e4369c27-80d8-44da-96e5-d7302ee347f8)
+    )
+    (pin "EN" input (at 113.03 118.11 180)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid b7638c8c-dd7b-4a7a-824a-59868b16c643)
+    )
+    (pin "PER_POWER" input (at 146.05 120.65 0)
+      (effects (font (size 1.27 1.27)) (justify right))
+      (uuid aa0787f5-acda-4213-847c-b9c01839095b)
+    )
+  )
+
+  (sheet (at 113.03 142.24) (size 33.02 20.32) (fields_autoplaced)
+    (stroke (width 0.001) (type solid) (color 132 0 132 1))
+    (fill (color 72 72 72 1.0000))
+    (uuid 77de7b9e-b79d-47ce-9bcc-fa93ceb69146)
+    (property "Sheet name" "Power_supply_5V" (id 0) (at 113.03 141.6043 0)
+      (effects (font (size 1.27 1.27)) (justify left bottom))
+    )
+    (property "Sheet file" "Power_supply.kicad_sch" (id 1) (at 113.03 163.0687 0)
+      (effects (font (size 1.27 1.27)) (justify left top))
+    )
+    (pin "IN" input (at 113.03 148.59 180)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid 5d92394a-92d5-463e-a6aa-1513d94bec68)
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+    (pin "OUT" input (at 146.05 153.67 0)
+      (effects (font (size 1.27 1.27)) (justify right))
+      (uuid d01c7dc9-b723-476e-80cb-87791bd9805b)
+    )
+    (pin "I_SEN" input (at 146.05 146.05 0)
+      (effects (font (size 1.27 1.27)) (justify right))
+      (uuid b3e173dd-2594-4878-bdab-9f7b0c3822bb)
+    )
+    (pin "EN" input (at 113.03 156.21 180)
+      (effects (font (size 1.27 1.27)) (justify left))
+      (uuid 92e5d9f1-a66c-4573-8240-bafacd547895)
+    )
+    (pin "PER_POWER" input (at 146.05 160.02 0)
+      (effects (font (size 1.27 1.27)) (justify right))
+      (uuid f1d161ae-cd0c-4d1b-bf13-21bcd9b74411)
+    )
+  )
+)

modules/EPS/Solar_input.kicad_sch

@@ -0,0 +1,574 @@
+(kicad_sch (version 20210621) (generator eeschema)
+
+  (uuid 11cd2ff5-feed-4db2-af14-43763d29bc27)
+
+  (paper "A4")
+
+  (title_block
+    (title "BUTCube - EPS")
+    (date "2021-06-01")
+    (rev "v1.0")
+    (company "VUT - FIT(STRaDe) & FME(IAE & IPE)")
+    (comment 1 "Author: Petr Malaník")
+  )
+
+  (lib_symbols
+    (symbol "Connector_Generic_MountingPin:Conn_01x02_MountingPin" (pin_names (offset 1.016) hide) (in_bom yes) (on_board yes)
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+        (effects (font (size 1.27 1.27)))
+      )
+      (property "Value" "Conn_01x02_MountingPin" (id 1) (at 1.27 -5.08 0)
+        (effects (font (size 1.27 1.27)) (justify left))
+      )
+      (property "Footprint" "" (id 2) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "Datasheet" "~" (id 3) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_keywords" "connector" (id 4) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_description" "Generic connectable mounting pin connector, single row, 01x02, script generated (kicad-library-utils/schlib/autogen/connector/)" (id 5) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_fp_filters" "Connector*:*_1x??-1MP*" (id 6) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (symbol "Conn_01x02_MountingPin_1_1"
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+        )
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+          (number "1" (effects (font (size 1.27 1.27))))
+        )
+        (pin passive line (at -5.08 -2.54 0) (length 3.81)
+          (name "Pin_2" (effects (font (size 1.27 1.27))))
+          (number "2" (effects (font (size 1.27 1.27))))
+        )
+        (pin passive line (at 0 -7.62 90) (length 3.048)
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+          (number "MP" (effects (font (size 1.27 1.27))))
+        )
+      )
+    )
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+      )
+      (property "Value" "GND" (id 1) (at 0 -3.81 0)
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+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "Datasheet" "" (id 3) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_keywords" "power-flag" (id 4) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_description" "Power symbol creates a global label with name \"GND\" , ground" (id 5) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (symbol "GND_0_1"
+        (polyline
+          (pts
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+            (xy 0 -1.27)
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+      )
+      (symbol "GND_1_1"
+        (pin power_in line (at 0 0 270) (length 0) hide
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+          (number "1" (effects (font (size 1.27 1.27))))
+        )
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+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_keywords" "power-flag" (id 4) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_description" "Special symbol for telling ERC where power comes from" (id 5) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (symbol "PWR_FLAG_0_0"
+        (pin power_out line (at 0 0 90) (length 0)
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+          (number "1" (effects (font (size 1.27 1.27))))
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+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid be22c9c2-8d74-4cbc-8ae7-40f988e15cf0)
+  )
+
+  (text "Connection to half of every solar module.\nProtection agains reverse current flow\n	should be implented of panels."
+    (at 135.89 46.99 0)
+    (effects (font (size 1.27 1.27)) (justify left bottom))
+    (uuid 54263196-cae6-4b35-b11c-4925248adc36)
+  )
+
+  (hierarchical_label "SOLAR_OUT" (shape input) (at 106.68 49.53 0)
+    (effects (font (size 1.27 1.27)) (justify left))
+    (uuid 27b2cde5-c9c0-4877-afdb-277ca5eb1b2f)
+  )
+
+  (symbol (lib_id "power:PWR_FLAG") (at 102.87 49.53 0)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid afe2dd24-9acf-428c-8603-b260bc75b79c)
+    (property "Reference" "#FLG010" (id 0) (at 102.87 47.625 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Value" "PWR_FLAG" (id 1) (at 102.87 45.9254 0))
+    (property "Footprint" "" (id 2) (at 102.87 49.53 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "~" (id 3) (at 102.87 49.53 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 72f7e5ab-e70f-4549-a485-598a1d5c1346))
+  )
+
+  (symbol (lib_id "power:GND") (at 88.9 57.15 0)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid 6ebe803f-5eb6-49de-94b4-9951fce61f79)
+    (property "Reference" "#PWR0104" (id 0) (at 88.9 63.5 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Value" "GND" (id 1) (at 88.9 61.7126 0)
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+    (pin "1" (uuid b1d590b1-1d7d-4622-911d-357dc49143e6))
+  )
+
+  (symbol (lib_id "power:GND") (at 88.9 76.2 0)
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+    (uuid 383420f2-56fd-4a2d-bbf3-76ceb60f62a6)
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+      (effects (font (size 1.27 1.27)) hide)
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+  (symbol (lib_id "power:GND") (at 88.9 95.25 0)
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+    (property "Reference" "#PWR0106" (id 0) (at 88.9 101.6 0)
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+  )
+
+  (symbol (lib_id "power:GND") (at 88.9 114.3 0)
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+    (uuid 65a61411-1205-40aa-902e-07e546492efb)
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+    (pin "1" (uuid 3a69ff45-ccac-4ab1-8e5c-465dcd70abd5))
+  )
+
+  (symbol (lib_id "power:GND") (at 88.9 133.35 0)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid e4ccc808-02ca-4386-b889-ffcb5a12309f)
+    (property "Reference" "#PWR0108" (id 0) (at 88.9 139.7 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Value" "GND" (id 1) (at 88.9 137.9126 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Footprint" "" (id 2) (at 88.9 133.35 0)
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+    )
+    (pin "1" (uuid 9400b559-0c9b-453f-ad48-eeb0a2008e37))
+  )
+
+  (symbol (lib_id "power:GND") (at 88.9 152.4 0)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid bf5a0034-d362-42b0-a742-3b6168bd38d9)
+    (property "Reference" "#PWR0109" (id 0) (at 88.9 158.75 0)
+      (effects (font (size 1.27 1.27)) hide)
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modules/EPS/Stack_connector.kicad_sch

@@ -0,0 +1,693 @@
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+  (paper "A4")
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+  (title_block
+    (title "BUTCube - EPS")
+    (date "2021-06-01")
+    (rev "v1.0")
+    (company "VUT - FIT(STRaDe) & FME(IAE & IPE)")
+    (comment 1 "Author: Petr Malaník")
+  )
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+  )
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+    )
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+      (effects (font (size 1.27 1.27)) hide)
+    )
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+      (effects (font (size 1.27 1.27)) hide)
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+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 0c5387d3-b0fb-4628-b2c7-ffcddd1d8386))
+  )
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+    (property "Value" "Stack_connector" (id 1) (at 146.05 61.0385 0))
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+      (effects (font (size 1.27 1.27)) hide)
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+    (pin "4" (uuid 6f366878-7ce6-40c6-b785-e9f460e74784))
+    (pin "40" (uuid 9cfe4a2d-185a-4801-9f03-128416888328))
+    (pin "5" (uuid c2389357-4e74-48a1-8d59-cd5aba4337de))
+    (pin "6" (uuid f5b0b499-469a-4baa-9014-d1b1f909f934))
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+    (pin "9" (uuid deb4e572-5657-4888-8065-c3e8dd64aad3))
+  )
+)

modules/EPS/USB_power.kicad_sch

@@ -0,0 +1,292 @@
+(kicad_sch (version 20210621) (generator eeschema)
+
+  (uuid 11cd2ff5-feed-4db2-af14-43763d29bc27)
+
+  (paper "A4")
+
+  (title_block
+    (title "BUTCube - EPS")
+    (date "2021-06-01")
+    (rev "v1.0")
+    (company "VUT - FIT(STRaDe) & FME(IAE & IPE)")
+    (comment 1 "Author: Petr Malaník")
+  )
+
+  (lib_symbols
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+        (effects (font (size 1.27 1.27)))
+      )
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+      )
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+      )
+      (property "ki_keywords" "connector" (id 4) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_description" "Generic connectable mounting pin connector, single row, 01x04, script generated (kicad-library-utils/schlib/autogen/connector/)" (id 5) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_fp_filters" "Connector*:*_1x??-1MP*" (id 6) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
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+          )
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+        )
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+        )
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+          (number "3" (effects (font (size 1.27 1.27))))
+        )
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+          (name "Pin_4" (effects (font (size 1.27 1.27))))
+          (number "4" (effects (font (size 1.27 1.27))))
+        )
+        (pin passive line (at 0 -10.16 90) (length 3.048)
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+          (number "MP" (effects (font (size 1.27 1.27))))
+        )
+      )
+    )
+    (symbol "power:GND" (power) (pin_names (offset 0)) (in_bom yes) (on_board yes)
+      (property "Reference" "#PWR" (id 0) (at 0 -6.35 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "Value" "GND" (id 1) (at 0 -3.81 0)
+        (effects (font (size 1.27 1.27)))
+      )
+      (property "Footprint" "" (id 2) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "Datasheet" "" (id 3) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_keywords" "power-flag" (id 4) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_description" "Power symbol creates a global label with name \"GND\" , ground" (id 5) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (symbol "GND_0_1"
+        (polyline
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+          )
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+        )
+      )
+      (symbol "GND_1_1"
+        (pin power_in line (at 0 0 270) (length 0) hide
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+          (number "1" (effects (font (size 1.27 1.27))))
+        )
+      )
+    )
+    (symbol "power:PWR_FLAG" (power) (pin_numbers hide) (pin_names (offset 0) hide) (in_bom yes) (on_board yes)
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+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "Value" "PWR_FLAG" (id 1) (at 0 3.81 0)
+        (effects (font (size 1.27 1.27)))
+      )
+      (property "Footprint" "" (id 2) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
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+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_keywords" "power-flag" (id 4) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_description" "Special symbol for telling ERC where power comes from" (id 5) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (symbol "PWR_FLAG_0_0"
+        (pin power_out line (at 0 0 90) (length 0)
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+          (number "1" (effects (font (size 1.27 1.27))))
+        )
+      )
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+  )
+
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+  (junction (at 177.8 101.6) (diameter 0.9144) (color 0 0 0 0))
+  (junction (at 182.88 93.98) (diameter 0.9144) (color 0 0 0 0))
+
+  (wire (pts (xy 175.26 93.98) (xy 177.8 93.98))
+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid d5b2ee10-ee5c-4056-9f9b-0c39a2f4dd0f)
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+    (stroke (width 0) (type solid) (color 0 0 0 0))
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+  )
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+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid c2479a62-d903-451c-80d5-548b0cfca283)
+  )
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+    (stroke (width 0) (type solid) (color 0 0 0 0))
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+  )
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+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid d5b2ee10-ee5c-4056-9f9b-0c39a2f4dd0f)
+  )
+
+  (text "Protection and CC line configuration\nis part of Access port module"
+    (at 163.83 85.09 0)
+    (effects (font (size 1.27 1.27)) (justify left bottom))
+    (uuid 8bf22bb7-fb45-45aa-a207-b549e0f937a7)
+  )
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+    (effects (font (size 1.27 1.27)) (justify right bottom))
+    (uuid af384758-2600-45ae-80b0-bbd15d6dedbc)
+  )
+
+  (hierarchical_label "USB_POWER" (shape input) (at 186.69 93.98 0)
+    (effects (font (size 1.27 1.27) (thickness 0.254)) (justify left))
+    (uuid d94df75d-11e8-4075-95d1-64fd8e96579c)
+  )
+
+  (symbol (lib_id "power:PWR_FLAG") (at 182.88 93.98 0) (unit 1)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid 23bac90a-67ec-4f39-afbb-36799cd25092)
+    (property "Reference" "#FLG033" (id 0) (at 182.88 92.075 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Value" "PWR_FLAG" (id 1) (at 182.88 90.3754 0))
+    (property "Footprint" "" (id 2) (at 182.88 93.98 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
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+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 081d3d27-811c-4998-b28c-3b4f32509769))
+  )
+
+  (symbol (lib_id "power:GND") (at 170.18 106.68 0) (unit 1)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid f3179a51-ce67-4f96-9a0f-40ef7668e229)
+    (property "Reference" "#PWR0281" (id 0) (at 170.18 113.03 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Value" "GND" (id 1) (at 170.18 111.2426 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Footprint" "" (id 2) (at 170.18 106.68 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
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+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 12787b8a-9625-4d08-b355-7188b8d6818d))
+  )
+
+  (symbol (lib_id "power:GND") (at 177.8 104.14 0) (unit 1)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid dae00e47-3713-4b7a-82c5-13bba541887c)
+    (property "Reference" "#PWR0282" (id 0) (at 177.8 110.49 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
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+      (effects (font (size 1.27 1.27)) hide)
+    )
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+  )
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+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid 54e74f5e-f1ac-457c-a393-65946b8321d6)
+    (property "Reference" "J24" (id 0) (at 172.212 88.7434 0))
+    (property "Value" "USB_POWER" (id 1) (at 172.212 91.5185 0))
+    (property "Footprint" "TCY_connectors:Amphenol_10114830-11103LF_1x04_P1.25mm_Horizontal" (id 2) (at 170.18 96.52 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
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+    (pin "3" (uuid 0069f29f-ed04-4799-91ba-a9a36ab9b8ec))
+    (pin "4" (uuid 6c96bbbc-f03e-446d-a398-cdb5b3e6142d))
+    (pin "MP" (uuid ce36b827-8cad-4e9c-98f5-5d4d5aa634f1))
+  )
+)

modules/EPS/calc.ipynb

@@ -0,0 +1,372 @@
+{
+ "metadata": {
+  "language_info": {
+   "codemirror_mode": {
+    "name": "ipython",
+    "version": 3
+   },
+   "file_extension": ".py",
+   "mimetype": "text/x-python",
+   "name": "python",
+   "nbconvert_exporter": "python",
+   "pygments_lexer": "ipython3",
+   "version": "3.8.10"
+  },
+  "orig_nbformat": 4,
+  "kernelspec": {
+   "name": "python3",
+   "display_name": "Python 3.8.10 64-bit"
+  },
+  "interpreter": {
+   "hash": "31f2aee4e71d21fbe5cf8b01ff0e069b9275f58929596ceb00d14d90e3e16cd6"
+  }
+ },
+ "nbformat": 4,
+ "nbformat_minor": 2,
+ "cells": [
+  {
+   "cell_type": "code",
+   "execution_count": 27,
+   "source": [
+    "# Current sense aplifier preliminary design \n",
+    "\n",
+    "supply_voltage = 4.2\n",
+    "max_current = 2.0\n",
+    "acceptable_power_loss = 0.1 #watts\n",
+    "amp_ratios = [50,100,200]\n",
+    "sense_voltage = 3.3\n",
+    "\n",
+    "adc_resolution = 4096\n",
+    "divider_R1 = 100 # kilo-ohms\n",
+    "\n",
+    "max_power = supply_voltage * max_current\n",
+    "\n",
+    "acceptable_voltage_drop = acceptable_power_loss / supply_voltage\n",
+    "print(\"Acceptable voltage drop: {}V\".format(round(acceptable_voltage_drop,2)))\n",
+    "power_loss_percentage = acceptable_power_loss/max_power*100\n",
+    "print(\"Power loss percentage: {}%\".format(round(power_loss_percentage,2)))\n",
+    "\n",
+    "amp_ratios.sort()\n",
+    "\n",
+    "print(\"--------------- Full - range ---------------\")\n",
+    "for ratio in amp_ratios:\n",
+    "    ideal_resistor = supply_voltage / ratio / max_current\n",
+    "    power_loss = ideal_resistor * max_current**2\n",
+    "\n",
+    "    print(\"Ideal resistor: {}R\".format(ideal_resistor))\n",
+    "    print(\"Power loss: {}W\".format(power_loss))\n",
+    "    print(\"--------------------------------------------\")\n",
+    "\n",
+    "if sense_voltage < supply_voltage:\n",
+    "    divider_R2 = round((sense_voltage * divider_R1) / (supply_voltage - sense_voltage),3)\n",
+    "    print(\"Output voltage divider: R1 = {} kΩ, R2 = {} kΩ\".format(divider_R1,divider_R2))\n",
+    "\n",
+    "max_output_voltage = min(supply_voltage, supply_voltage)\n",
+    "resolution = round(max_current/adc_resolution*1000,2)\n",
+    "print(\"Resolution: {}mA\".format(resolution))\n",
+    "\n",
+    "print(\"---------------- Acceptable ----------------\")\n",
+    "acceptable_resistor = acceptable_voltage_drop/max_current\n",
+    "power_loss = acceptable_resistor * max_current**2\n",
+    "\n",
+    "ideal_ratio = None\n",
+    "for ratio in amp_ratios:\n",
+    "    if acceptable_voltage_drop * ratio < supply_voltage:\n",
+    "        ideal_ratio = ratio\n",
+    "    else:\n",
+    "        break\n",
+    "\n",
+    "max_output_voltage = acceptable_voltage_drop * ideal_ratio\n",
+    "print(\"Maximal output voltage: {}V\".format(max_output_voltage))\n",
+    "\n",
+    "if sense_voltage < max_output_voltage:\n",
+    "    divider_R2 = round((sense_voltage * divider_R1) / (max_output_voltage - sense_voltage),3)\n",
+    "    print(\"Output voltage divider: R1 = {} kΩ, R2 = {} kΩ\".format(divider_R1,divider_R2))\n",
+    "\n",
+    "resolution = round(max_current/adc_resolution*1000,2)\n",
+    "\n",
+    "print(\"Ideal ratio: {}\".format(ideal_ratio))\n",
+    "print(\"Ideal resistor: {}R\".format(acceptable_resistor))\n",
+    "print(\"Power loss: {}W\".format(power_loss))\n",
+    "print(\"Resolution: {}mA\".format(resolution))"
+   ],
+   "outputs": [
+    {
+     "output_type": "stream",
+     "name": "stdout",
+     "text": [
+      "Acceptable voltage drop: 0.02V\n",
+      "Power loss percentage: 1.19%\n",
+      "--------------- Full - range ---------------\n",
+      "Ideal resistor: 0.042R\n",
+      "Power loss: 0.168W\n",
+      "--------------------------------------------\n",
+      "Ideal resistor: 0.021R\n",
+      "Power loss: 0.084W\n",
+      "--------------------------------------------\n",
+      "Ideal resistor: 0.0105R\n",
+      "Power loss: 0.042W\n",
+      "--------------------------------------------\n",
+      "Output voltage divider: R1 = 100 kΩ, R2 = 366.667 kΩ\n",
+      "Resolution: 0.49mA\n",
+      "---------------- Acceptable ----------------\n",
+      "Maximal output voltage: 2.380952380952381V\n",
+      "Ideal ratio: 100\n",
+      "Ideal resistor: 0.011904761904761904R\n",
+      "Power loss: 0.047619047619047616W\n",
+      "Resolution: 0.49mA\n"
+     ]
+    }
+   ],
+   "metadata": {}
+  },
+  {
+   "cell_type": "code",
+   "execution_count": 4,
+   "source": [
+    "# Current sense aplifier design evaluating\n",
+    "\n",
+    "supply_voltage = 2.8\n",
+    "sense_voltage = 3.3\n",
+    "sense_resistor = 0.01\n",
+    "amp_ratio = 50\n",
+    "divider_R1  = 100 # kilo-ohms\n",
+    "selected_R2 = 270 # kilo-ohms\n",
+    "\n",
+    "adc_resolution = 4096\n",
+    "\n",
+    "max_current = supply_voltage / sense_resistor / amp_ratio\n",
+    "power_disipation = sense_resistor * max_current**2\n",
+    "voltage_drop = sense_resistor * max_current\n",
+    "resolution = round(max_current/adc_resolution*1000,3)\n",
+    "\n",
+    "\n",
+    "print(\"Maximal current: {}A\".format(round(max_current,2)))\n",
+    "print(\"Maximal power disipation: {}W\".format(round(power_disipation,2)))\n",
+    "print(\"Maximal voltage drop: {}V\".format(round(voltage_drop,2)))\n",
+    "\n",
+    "if sense_voltage > supply_voltage:\n",
+    "    resolution *= 1 / (supply_voltage/sense_voltage)\n",
+    "\n",
+    "print(\"Resolution: {} mA\".format(round(resolution,2)))\n",
+    "\n",
+    "if sense_voltage < supply_voltage:\n",
+    "    divider_R2 = round((sense_voltage * divider_R1) / (supply_voltage - sense_voltage),2)\n",
+    "    print(\"Output voltage divider: R1 = {} kΩ, R2 = {} kΩ\".format(divider_R1,divider_R2))\n",
+    "    divider_leakage = supply_voltage / ((divider_R1 + divider_R2)*1000)\n",
+    "    print(\"Maximum divider leakage: {} uA\".format(round(divider_leakage*1000000),2))\n",
+    "\n",
+    "print(\"---------------- Selected divider ----------------\")\n",
+    "maximum_divider_voltage = supply_voltage * (selected_R2 / (selected_R2 + divider_R1))\n",
+    "print(\"Maximum divider voltage: {} V\".format(round(maximum_divider_voltage,2)))\n",
+    "resolution *= 1 / (maximum_divider_voltage/sense_voltage)\n",
+    "print(\"Resolution: {} mA\".format(round(resolution,2)))"
+   ],
+   "outputs": [
+    {
+     "output_type": "stream",
+     "name": "stdout",
+     "text": [
+      "Maximal current: 2.8A\n",
+      "Maximal power disipation: 0.08W\n",
+      "Maximal voltage drop: 0.03V\n",
+      "Resolution: 0.81 mA\n",
+      "---------------- Selected divider ----------------\n",
+      "Maximum divider voltage: 2.04 V\n",
+      "Resolution: 1.3 mA\n"
+     ]
+    }
+   ],
+   "metadata": {}
+  },
+  {
+   "cell_type": "code",
+   "execution_count": 1,
+   "source": [
+    "# Battery heating wire calculator\n",
+    "import math\n",
+    "\n",
+    "bat_diameter = 21 # in mm\n",
+    "heating_power = 2 # watts\n",
+    "voltage = 3.7\n",
+    "wire_resistance = 5.5 # per meter\n",
+    "\n",
+    "wrap_length = bat_diameter * math.pi / 1000\n",
+    "current = heating_power / voltage\n",
+    "resistance = voltage / current\n",
+    "length = resistance / wire_resistance\n",
+    "wraps = length / wrap_length\n",
+    "\n",
+    "print(\"Length: {}\".format(length))\n",
+    "print(\"Wraps:  {}\".format(wraps))"
+   ],
+   "outputs": [
+    {
+     "output_type": "stream",
+     "name": "stdout",
+     "text": [
+      "Length: 1.2445454545454548\n",
+      "Wraps:  18.86433914223418\n"
+     ]
+    }
+   ],
+   "metadata": {}
+  },
+  {
+   "cell_type": "code",
+   "execution_count": 24,
+   "source": [
+    "# LTC4231\n",
+    "\n",
+    "# Voltage settings\n",
+    "undervoltage_rising = 3\n",
+    "undervoltage_falling = 2.9\n",
+    "overvoltage_falling = 4.4\n",
+    "input_voltage = 3.7\n",
+    "\n",
+    "# Design parameters\n",
+    "resistance_total = 2000000\n",
+    "overcurrent_threshold = 5\n",
+    "soa_time = 0.0005\n",
+    "\n",
+    "# Sence voltage constants from LTC4231 datasheet\n",
+    "sense_voltage_slow = 0.05\n",
+    "sense_voltage_min  = 0.065\n",
+    "sense_voltage_fast = 0.08\n",
+    "sense_voltage_max  = 0.09\n",
+    "\n",
+    "R4 = (0.795/overvoltage_falling) * resistance_total\n",
+    "R3 = ((overvoltage_falling/undervoltage_rising) - 1) * R4\n",
+    "R2 = ((undervoltage_rising/undervoltage_falling) - 1) * (overvoltage_falling/undervoltage_rising) * R4\n",
+    "R1 = ((overvoltage_falling/0.795) - 1) * R4 - R3 - R2\n",
+    "\n",
+    "print(\"R4 value = {}k\".format(round(R4/1000)))\n",
+    "print(\"R3 value = {}k\".format(round(R3/1000)))\n",
+    "print(\"R2 value = {}k\".format(round(R2/1000)))\n",
+    "print(\"R1 value = {}k\".format(round(R1/1000)))\n",
+    "\n",
+    "divider_leakage = input_voltage/(R1 + R2 + R3 + R4)\n",
+    "sense_resistor = sense_voltage_slow/overcurrent_threshold\n",
+    "current_limit_fast = sense_voltage_fast / sense_resistor\n",
+    "sense_resistor_power = sense_resistor * current_limit_fast**2\n",
+    "current_limit_max = sense_voltage_max/sense_resistor\n",
+    "\n",
+    "print(\"Divider leakage = {} uA\".format(divider_leakage*1000000))\n",
+    "print(\"Sensing resistor = {} mR\".format(sense_resistor*1000))\n",
+    "print(\"Sensing resistor power dissipation = {} W\".format(sense_resistor_power))\n",
+    "print(\"Worst case current = {} A\".format(current_limit_max))\n",
+    "\n",
+    "load_capacitor_charge = (0.0001 * input_voltage) / (sense_voltage_min / sense_resistor)\n",
+    "mosfet_dissipation = input_voltage * current_limit_max\n",
+    "overcurrent_triptime = (soa_time - load_capacitor_charge)/4 + load_capacitor_charge\n",
+    "timer_capacitor = overcurrent_triptime/input_voltage\n",
+    "\n",
+    "print(\"OC timer charge = {} ms\".format(round(load_capacitor_charge*1000,2)))\n",
+    "print(\"MOSFET power dissipation = {} W\".format(round(mosfet_dissipation,2)))\n",
+    "print(\"Time to OC protection trip = {} ms\".format(round(overcurrent_triptime*1000,2)))\n",
+    "print(\"Timer capacitor C_T value = {} nF\".format(round(timer_capacitor*1000000,2)))"
+   ],
+   "outputs": [
+    {
+     "output_type": "stream",
+     "name": "stdout",
+     "text": [
+      "R4 value = 361k\n",
+      "R3 value = 169k\n",
+      "R2 value = 18k\n",
+      "R1 value = 1452k\n",
+      "Divider leakage = 1.85 uA\n",
+      "Sensing resistor = 10.0 mR\n",
+      "Sensing resistor power dissipation = 0.64 W\n",
+      "Worst case current = 9.0 A\n",
+      "OC timer charge = 0.06 ms\n",
+      "MOSFET power dissipation = 33.3 W\n",
+      "Time to OC protection trip = 0.17 ms\n",
+      "Timer capacitor C_T value = 45.32 nF\n"
+     ]
+    }
+   ],
+   "metadata": {}
+  },
+  {
+   "cell_type": "code",
+   "execution_count": 22,
+   "source": [
+    "#BQ25798\n",
+    "\n",
+    "## Termistor settings\n",
+    "# JEITA profile temperature points\n",
+    "temp_T1 = 0     # °C\n",
+    "temp_T5 = 60\n",
+    "\n",
+    "# NTC resistance at temperature points\n",
+    "termistor_at_T1 = 29250.0\n",
+    "termistor_at_T5 = 2900.0\n",
+    "\n",
+    "# Voltage of temperature level in fraction of REGN voltage\n",
+    "temp_T1_threshold = 0.733\n",
+    "temp_T5_threshold = 0.342\n",
+    "\n",
+    "resistor_RT2 = (termistor_at_T1*termistor_at_T5 * ((1.0/temp_T5_threshold)-(1.0/temp_T1_threshold))) / ((termistor_at_T1 * ((1.0/temp_T1_threshold) - 1))-(termistor_at_T5 * ((1.0/temp_T5_threshold) - 1)))\n",
+    "resistor_RT1 = ((1.0/temp_T1_threshold) - 1) / ( (1.0 / resistor_RT2) + (1.0/termistor_at_T1) )\n",
+    "\n",
+    "print(\"Battery termistor resistor network\")\n",
+    "print(\"RT1 = {} k\".format(round(resistor_RT1/1000,2)))\n",
+    "print(\"RT2 = {} k\".format(round(resistor_RT2/1000,2)))\n",
+    "\n",
+    "## Input current limitation\n",
+    "maximal_input_current_draw = 0.9 # in Amp\n",
+    "divider_R1 = 100 # in kOhms\n",
+    "\n",
+    "voltage_REGN = 4.8\n",
+    "\n",
+    "voltage_ILIM = 1 + 0.8 * maximal_input_current_draw\n",
+    "divider_R2 = round((voltage_ILIM * divider_R1) / (voltage_REGN - voltage_ILIM),3)\n",
+    "print(\"ILIM voltage divider: R1 = {} kΩ, R2 = {} kΩ\".format(divider_R1,divider_R2))\n",
+    "\n",
+    "\n"
+   ],
+   "outputs": [
+    {
+     "output_type": "stream",
+     "name": "stdout",
+     "text": [
+      "Battery termistor resistor network\n",
+      "RT1 = 5.02 k\n",
+      "RT2 = 26.07 k\n",
+      "ILIM voltage divider: R1 = 100 kΩ, R2 = 55.844 kΩ\n"
+     ]
+    }
+   ],
+   "metadata": {}
+  },
+  {
+   "cell_type": "code",
+   "execution_count": 42,
+   "source": [
+    "# TPS6300\n",
+    "\n",
+    "output_voltages = [1.8,3.3,5.0]\n",
+    "resistor_R2 = 200 # in kOhms, recommended 100-500 kR\n",
+    "\n",
+    "feedback_voltage = 0.5 # V\n",
+    "\n",
+    "for output_voltage in output_voltages:\n",
+    "    resistor_R1 = resistor_R2 * (output_voltage/feedback_voltage-1)\n",
+    "    print(\"Resistor R2 for output voltage {} V is: {} kΩ\".format(output_voltage, resistor_R1))\n"
+   ],
+   "outputs": [
+    {
+     "output_type": "stream",
+     "name": "stdout",
+     "text": [
+      "Resistor R2 for output voltage 1.8 V is: 520.0 kΩ\n",
+      "Resistor R2 for output voltage 3.3 V is: 1120.0 kΩ\n",
+      "Resistor R2 for output voltage 5.0 V is: 1800.0 kΩ\n"
+     ]
+    }
+   ],
+   "metadata": {}
+  }
+ ]
+}

modules/EPS/fw/EPS.ioc

@@ -0,0 +1,296 @@
+#MicroXplorer Configuration settings - do not modify
+ADC1.Channel-1\#ChannelRegularConversion=ADC_CHANNEL_6
+ADC1.IPParameters=Rank-1\#ChannelRegularConversion,Channel-1\#ChannelRegularConversion,SamplingTime-1\#ChannelRegularConversion,OffsetNumber-1\#ChannelRegularConversion,NbrOfConversionFlag,master
+ADC1.NbrOfConversionFlag=1
+ADC1.OffsetNumber-1\#ChannelRegularConversion=ADC_OFFSET_NONE
+ADC1.Rank-1\#ChannelRegularConversion=1
+ADC1.SamplingTime-1\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5
+ADC1.master=1
+CAN1.BS1=CAN_BS1_1TQ
+CAN1.BS2=CAN_BS2_1TQ
+CAN1.CalculateBaudRate=1666666
+CAN1.CalculateTimeBit=600.00
+CAN1.CalculateTimeQuantum=200.0
+CAN1.IPParameters=CalculateTimeQuantum,CalculateTimeBit,CalculateBaudRate,BS1,BS2
+File.Version=6
+GPIO.groupedBy=Group By Peripherals
+I2C1.IPParameters=Timing
+I2C1.Timing=0x10909CEC
+KeepUserPlacement=false
+LPUART1.IPParameters=WordLength
+LPUART1.WordLength=UART_WORDLENGTH_8B
+Mcu.Family=STM32L4
+Mcu.IP0=ADC1
+Mcu.IP1=CAN1
+Mcu.IP2=DAC1
+Mcu.IP3=I2C1
+Mcu.IP4=LPUART1
+Mcu.IP5=NVIC
+Mcu.IP6=RCC
+Mcu.IP7=SPI3
+Mcu.IP8=SYS
+Mcu.IP9=USART1
+Mcu.IPNb=10
+Mcu.Name=STM32L452C(C-E)Ux
+Mcu.Package=UFQFPN48
+Mcu.Pin0=PC13
+Mcu.Pin1=PC14-OSC32_IN (PC14)
+Mcu.Pin10=PB0
+Mcu.Pin11=PB1
+Mcu.Pin12=PB2
+Mcu.Pin13=PB10
+Mcu.Pin14=PB11
+Mcu.Pin15=PB12
+Mcu.Pin16=PB13
+Mcu.Pin17=PB14
+Mcu.Pin18=PB15
+Mcu.Pin19=PA8
+Mcu.Pin2=PH0-OSC_IN (PH0)
+Mcu.Pin20=PA9
+Mcu.Pin21=PA10
+Mcu.Pin22=PA11
+Mcu.Pin23=PA12
+Mcu.Pin24=PA13 (JTMS/SWDIO)
+Mcu.Pin25=PA14 (JTCK/SWCLK)
+Mcu.Pin26=PA15 (JTDI)
+Mcu.Pin27=PB3 (JTDO/TRACESWO)
+Mcu.Pin28=PB4 (NJTRST)
+Mcu.Pin29=PB5
+Mcu.Pin3=PA1
+Mcu.Pin30=PB6
+Mcu.Pin31=PB7
+Mcu.Pin32=PH3-BOOT0 (BOOT0)
+Mcu.Pin33=PB8
+Mcu.Pin34=PB9
+Mcu.Pin35=VP_SYS_VS_Systick
+Mcu.Pin4=PA2
+Mcu.Pin5=PA3
+Mcu.Pin6=PA4
+Mcu.Pin7=PA5
+Mcu.Pin8=PA6
+Mcu.Pin9=PA7
+Mcu.PinsNb=36
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32L452CEUx
+MxCube.Version=6.2.1
+MxDb.Version=DB.6.0.21
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA1.GPIOParameters=GPIO_Label
+PA1.GPIO_Label=OUT_CUR
+PA1.Locked=true
+PA1.Signal=ADCx_IN6
+PA10.Mode=Asynchronous
+PA10.Signal=USART1_RX
+PA11.GPIOParameters=GPIO_Label
+PA11.GPIO_Label=RS_485_R_EN
+PA11.Locked=true
+PA11.Signal=GPIO_Output
+PA12.GPIOParameters=GPIO_Label
+PA12.GPIO_Label=RS_485_T_EN
+PA12.Locked=true
+PA12.Signal=GPIO_Output
+PA13\ (JTMS/SWDIO).Mode=Serial_Wire
+PA13\ (JTMS/SWDIO).Signal=SYS_JTMS-SWDIO
+PA14\ (JTCK/SWCLK).Mode=Serial_Wire
+PA14\ (JTCK/SWCLK).Signal=SYS_JTCK-SWCLK
+PA15\ (JTDI).GPIOParameters=GPIO_Label
+PA15\ (JTDI).GPIO_Label=ADC_CS
+PA15\ (JTDI).Locked=true
+PA15\ (JTDI).Signal=GPIO_Output
+PA2.GPIOParameters=GPIO_Label
+PA2.GPIO_Label=BAT_TEMP
+PA2.Signal=ADCx_IN7
+PA3.GPIOParameters=GPIO_Label
+PA3.GPIO_Label=NTC_REF
+PA3.Locked=true
+PA3.Signal=GPIO_Output
+PA4.GPIOParameters=GPIO_Label
+PA4.GPIO_Label=BAT_CHARGE
+PA4.Signal=COMP_DAC11_group
+PA5.GPIOParameters=GPIO_Label
+PA5.GPIO_Label=VBAT_EN
+PA5.Locked=true
+PA5.Signal=GPIO_Output
+PA6.GPIOParameters=GPIO_Label
+PA6.GPIO_Label=_5V_EN
+PA6.Locked=true
+PA6.Signal=GPIO_Output
+PA7.GPIOParameters=GPIO_Label
+PA7.GPIO_Label=_3V3_EN
+PA7.Locked=true
+PA7.Signal=GPIO_Output
+PA8.GPIOParameters=GPIO_Label
+PA8.GPIO_Label=LED2
+PA8.Locked=true
+PA8.Signal=GPIO_Output
+PA9.Mode=Asynchronous
+PA9.Signal=USART1_TX
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=_1V8_EN
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PB1.GPIOParameters=GPIO_Label
+PB1.GPIO_Label=BAT_IRQ
+PB1.Locked=true
+PB1.Signal=GPXTI1
+PB10.Mode=Asynchronous
+PB10.Signal=LPUART1_RX
+PB11.Mode=Asynchronous
+PB11.Signal=LPUART1_TX
+PB12.Mode=CAN_Activate
+PB12.Signal=CAN1_RX
+PB13.Mode=CAN_Activate
+PB13.Signal=CAN1_TX
+PB14.GPIOParameters=GPIO_Label
+PB14.GPIO_Label=CAN_RS
+PB14.Locked=true
+PB14.Signal=GPIO_Output
+PB15.GPIOParameters=GPIO_Label
+PB15.GPIO_Label=LED1
+PB15.Locked=true
+PB15.Signal=GPIO_Output
+PB2.GPIOParameters=GPIO_Label
+PB2.GPIO_Label=BAT_ALERT
+PB2.Locked=true
+PB2.Signal=GPXTI2
+PB3\ (JTDO/TRACESWO).Mode=Full_Duplex_Master
+PB3\ (JTDO/TRACESWO).Signal=SPI3_SCK
+PB4\ (NJTRST).Mode=Full_Duplex_Master
+PB4\ (NJTRST).Signal=SPI3_MISO
+PB5.Mode=Full_Duplex_Master
+PB5.Signal=SPI3_MOSI
+PB6.Mode=I2C
+PB6.Signal=I2C1_SCL
+PB7.Mode=I2C
+PB7.Signal=I2C1_SDA
+PB8.GPIOParameters=GPIO_Label
+PB8.GPIO_Label=HEAT_FAULT
+PB8.Locked=true
+PB8.Signal=GPXTI8
+PB9.GPIOParameters=GPIO_Label
+PB9.GPIO_Label=HEAT_EN
+PB9.Locked=true
+PB9.Signal=GPIO_Output
+PC13.GPIOParameters=GPIO_Label
+PC13.GPIO_Label=WDG_RESET
+PC13.Locked=true
+PC13.Signal=GPIO_Output
+PC14-OSC32_IN\ (PC14).Mode=LSE-External-Clock-Source
+PC14-OSC32_IN\ (PC14).Signal=RCC_OSC32_IN
+PH0-OSC_IN\ (PH0).Mode=HSE-External-Clock-Source
+PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN
+PH3-BOOT0\ (BOOT0).GPIOParameters=GPIO_Label
+PH3-BOOT0\ (BOOT0).GPIO_Label=FRAM_CS
+PH3-BOOT0\ (BOOT0).Locked=true
+PH3-BOOT0\ (BOOT0).Signal=GPIO_Output
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32L452CEUx
+ProjectManager.FirmwarePackage=STM32Cube FW_L4 V1.17.0
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=0
+ProjectManager.MainLocation=Core/Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=EPS.ioc
+ProjectManager.ProjectName=EPS
+ProjectManager.RegisterCallBack=
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8.32
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_ADC1_Init-ADC1-false-HAL-true,4-MX_CAN1_Init-CAN1-false-HAL-true,5-MX_DAC1_Init-DAC1-false-HAL-true,6-MX_I2C1_Init-I2C1-false-HAL-true,7-MX_LPUART1_UART_Init-LPUART1-false-HAL-true,8-MX_USART1_UART_Init-USART1-false-HAL-true,9-MX_SPI3_Init-SPI3-false-HAL-true
+RCC.ADCFreq_Value=40000000
+RCC.AHBFreq_Value=80000000
+RCC.APB1Freq_Value=80000000
+RCC.APB1TimFreq_Value=80000000
+RCC.APB2Freq_Value=80000000
+RCC.APB2TimFreq_Value=80000000
+RCC.CortexFreq_Value=80000000
+RCC.DFSDMFreq_Value=80000000
+RCC.FCLKCortexFreq_Value=80000000
+RCC.FamilyName=M
+RCC.HCLKFreq_Value=80000000
+RCC.HSE_VALUE=20000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=80000000
+RCC.I2C2Freq_Value=80000000
+RCC.I2C3Freq_Value=80000000
+RCC.I2C4Freq_Value=80000000
+RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,DFSDMFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,MSI_VALUE,PLLM,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSourceVirtual,PWRFreq_Value,RNGFreq_Value,SAI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value
+RCC.LPTIM1Freq_Value=80000000
+RCC.LPTIM2Freq_Value=80000000
+RCC.LPUART1Freq_Value=80000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=80000000
+RCC.MSI_VALUE=4000000
+RCC.PLLM=2
+RCC.PLLN=16
+RCC.PLLPoutputFreq_Value=22857142.85714286
+RCC.PLLQoutputFreq_Value=80000000
+RCC.PLLRCLKFreq_Value=80000000
+RCC.PLLSAI1PoutputFreq_Value=11428571.42857143
+RCC.PLLSAI1QoutputFreq_Value=40000000
+RCC.PLLSAI1RoutputFreq_Value=40000000
+RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
+RCC.PWRFreq_Value=80000000
+RCC.RNGFreq_Value=40000000
+RCC.SAI1Freq_Value=11428571.42857143
+RCC.SYSCLKFreq_VALUE=80000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.UART4Freq_Value=80000000
+RCC.USART1Freq_Value=80000000
+RCC.USART2Freq_Value=80000000
+RCC.USART3Freq_Value=80000000
+RCC.USBFreq_Value=40000000
+RCC.VCOInputFreq_Value=10000000
+RCC.VCOOutputFreq_Value=160000000
+RCC.VCOSAI1OutputFreq_Value=80000000
+SH.ADCx_IN6.0=ADC1_IN6,IN6-Single-Ended
+SH.ADCx_IN6.ConfNb=1
+SH.ADCx_IN7.0=ADC1_IN7,IN7-Single-Ended
+SH.ADCx_IN7.ConfNb=1
+SH.COMP_DAC11_group.0=DAC1_OUT1,DAC_OUT1
+SH.COMP_DAC11_group.ConfNb=1
+SH.GPXTI1.0=GPIO_EXTI1
+SH.GPXTI1.ConfNb=1
+SH.GPXTI2.0=GPIO_EXTI2
+SH.GPXTI2.ConfNb=1
+SH.GPXTI8.0=GPIO_EXTI8
+SH.GPXTI8.ConfNb=1
+SPI3.CalculateBaudRate=40.0 MBits/s
+SPI3.Direction=SPI_DIRECTION_2LINES
+SPI3.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate
+SPI3.Mode=SPI_MODE_MASTER
+SPI3.VirtualType=VM_MASTER
+USART1.IPParameters=VirtualMode-Asynchronous
+USART1.VirtualMode-Asynchronous=VM_ASYNC
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom

modules/Solar_module_XY/.gitignore

@@ -1 +1,2 @@
 Solar_module_XY-backups
+gerbers/

modules/Solar_module_XY/Solar_module_XY.kicad_prl

@@ -1,6 +1,6 @@
 {
   "board": {
-    "active_layer": 31,
+    "active_layer": 36,
     "active_layer_preset": "",
     "auto_track_width": true,
     "hidden_nets": [],

modules/Solar_module_XY/Solar_module_XY.kicad_pro

@@ -55,7 +55,40 @@
           "width": 0.0
         }
       ],
-      "drc_exclusions": [],
+      "drc_exclusions": [
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+        "copper_edge_clearance|116934456|88502140|12601d4d-9f6b-441d-bd90-fada6e4b87e5|3e42eef1-eeb6-4aff-96dc-99e9ebc36744",
+        "copper_edge_clearance|117000001|99500001|4c3fd363-83bd-4872-a414-a437b42b446f|211bf903-aa51-45df-8f81-81e60a0fdcb9",
+        "copper_edge_clearance|117350000|49500001|2f6d15c7-4477-4ad9-a200-c7308ef4b846|bd8e96df-a568-42d2-9127-3f9151a0b1d3",
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+        "copper_edge_clearance|119000001|88500001|43a9bf09-97ca-4edd-9732-e421ab7ff713|9fd407b7-d7b5-4734-9240-5955d7ffea2a",
+        "copper_edge_clearance|119065546|99497862|3181f291-c5fb-41cb-a3ce-c0b352ce52ff|b6d9f025-7762-4469-961b-1e8ac433ef1b",
+        "copper_edge_clearance|129997862|116434456|5f9f3e52-3a57-4b5d-b25a-149abc970f24|9a76a1db-3449-4642-9a76-6cd7d00993b2",
+        "copper_edge_clearance|129997862|132934456|00e6beb7-1e10-497b-988c-c94ca5df12b1|ea5b6a1f-0336-4b12-89e2-514c3e35accf",
+        "copper_edge_clearance|129997862|52934456|e03c1ce5-98b0-456b-9561-277c930a2ea5|8de68402-e332-40ca-af61-6819171c2caa",
+        "copper_edge_clearance|129997862|69434456|5c9228a6-a03b-4ba7-b25b-d9626c5d0c7e|ddaa87cf-886c-4955-b20a-4ce9c579558e",
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+        "copper_edge_clearance|130000001|54650000|96ae93f8-dc51-43ba-baf5-c024f2ea8338|19183b5b-a7c2-4cd4-b516-db96b706c68b",
+        "copper_edge_clearance|130000001|71150000|9fa21e4c-ed0f-42c6-8437-e7a91a901df1|b1a6c97b-29d1-4507-8619-cdfb147f5875",
+        "copper_edge_clearance|169000001|116850000|b552cb4c-5e26-47d2-a7dd-70ddf83450de|e9c928a4-0cad-4d84-9ac0-1660e3368772",
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+        "copper_edge_clearance|169000001|53350000|030ef28a-29d4-4f58-92e8-740bf14ab01d|53348628-da08-49dd-aeb9-2a3713eb6ef9",
+        "copper_edge_clearance|169000001|69850000|efc20dda-f6f4-40c5-8d73-6f92846985c3|33afc8e0-1832-443b-b2ec-75f4e8f27ef0",
+        "copper_edge_clearance|169000001|71150000|efc20dda-f6f4-40c5-8d73-6f92846985c3|40a5b2cd-9ef0-44f6-9ec3-e731a817a511",
+        "copper_edge_clearance|169002140|118565546|c9d18ef9-6ceb-494a-bd16-bbde67e6ee7e|6e1847ce-cdfb-4d7c-892e-e057035165e7",
+        "copper_edge_clearance|169002140|135065546|640ecc8f-4847-4dfd-b9bc-f4992f4fe153|1dc2c3f1-276a-4de4-b0d2-7a9496cabab8",
+        "copper_edge_clearance|169002140|55065546|22ffcec7-c46b-4002-84e5-0af591b2b6ed|822788ca-96f7-43aa-958a-9d169661e9bd",
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+        "copper_edge_clearance|180000001|99500001|488c867e-a049-4c6d-9b5d-2265700d3176|00f0d83b-a1b8-4618-83ab-5651ce18eb75",
+        "copper_edge_clearance|180350000|138500001|9abcfb7c-fa8b-43a3-be55-1a2e51209738|123d0546-b585-4c58-8a1f-4204ee7cf2e0",
+        "copper_edge_clearance|180350000|88500001|a60d4a6f-bbf9-4b44-9f0c-7dec92f1ce58|79a58f44-63ed-46e6-a5c2-8a74d9b89481",
+        "copper_edge_clearance|181650000|138500001|9abcfb7c-fa8b-43a3-be55-1a2e51209738|2691039d-2c91-4e21-a062-099735c86c25",
+        "copper_edge_clearance|181650000|99500001|85d55c39-c34c-41c0-bc1f-dbfb726f47a1|3a26b561-357b-4837-93af-793d91125af3",
+        "copper_edge_clearance|182000001|88500001|8749c304-9e63-4b89-a582-447b685a9a75|f4f0d1cb-c307-4949-a6ba-9229d02342bc",
+        "copper_edge_clearance|182065546|49497862|7986647a-bda0-4498-8db8-01205c46a3c4|74fe8c6c-e22a-475f-9122-ef9a6763b49a"
+      ],
       "meta": {
         "version": 2
       },
@@ -69,6 +102,7 @@
         "drill_out_of_range": "error",
         "duplicate_footprints": "warning",
         "extra_footprint": "warning",
+        "footprint_type_mismatch": "error",
         "hole_clearance": "error",
         "hole_near_hole": "error",
         "invalid_outline": "error",
@@ -87,6 +121,7 @@
         "silk_over_copper": "error",
         "silk_overlap": "error",
         "skew_out_of_range": "error",
+        "through_hole_pad_without_hole": "error",
         "too_many_vias": "error",
         "track_dangling": "warning",
         "track_width": "error",
@@ -315,6 +350,7 @@
     ],
     "rule_severities": {
       "bus_definition_conflict": "error",
+      "bus_entry_needed": "error",
       "bus_label_syntax": "error",
       "bus_to_bus_conflict": "error",
       "bus_to_net_conflict": "error",
@@ -371,7 +407,7 @@
       }
     ],
     "meta": {
-      "version": 1
+      "version": 2
     },
     "net_colors": null
   },
@@ -384,9 +420,10 @@
       "step": "Solar_module_XY.step",
       "vrml": ""
     },
-    "page_layout_descr_file": "/home/petr/work/butcube/kicad_page_layout.kicad_wks"
+    "page_layout_descr_file": "/home/petr/work/butcube/resources/kicad_page_layout.kicad_wks"
   },
   "schematic": {
+    "annotate_start_num": 0,
     "drawing": {
       "default_bus_thickness": 12.0,
       "default_junction_size": 40.0,
@@ -400,23 +437,26 @@
       "intersheets_ref_show": false,
       "intersheets_ref_suffix": "",
       "junction_size_choice": 3,
+      "label_size_ratio": 0.3,
       "pin_symbol_size": 25.0,
       "text_offset_ratio": 0.3
     },
     "legacy_lib_dir": "",
     "legacy_lib_list": [],
     "meta": {
-      "version": 0
+      "version": 1
     },
     "net_format_name": "",
     "ngspice": {
+      "fix_include_paths": true,
+      "fix_passive_vals": false,
       "meta": {
         "version": 0
       },
       "model_mode": 0,
       "workbook_filename": ""
     },
-    "page_layout_descr_file": "/home/petr/work/butcube/kicad_page_layout.kicad_wks",
+    "page_layout_descr_file": "/home/petr/work/butcube/resources/kicad_page_layout.kicad_wks",
     "plot_directory": "",
     "spice_adjust_passive_values": false,
     "spice_external_command": "spice \"%I\"",
@@ -435,14 +475,6 @@
     [
       "22eee9c3-c9d0-4d93-be59-be741d8b9bee",
       "Solar_unit_1"
-    ],
-    [
-      "53e9ff4e-ea34-4280-9514-a003468a008c",
-      "Solar_unit_4"
-    ],
-    [
-      "dcd95010-e092-4767-a18b-c97e6c93d4a6",
-      "Solar_unit_3"
     ]
   ],
   "text_variables": {}

modules/Solar_module_XY/Solar_unit.kicad_sch

@@ -1,12 +1,12 @@
-(kicad_sch (version 20210406) (generator eeschema)
+(kicad_sch (version 20211123) (generator eeschema)
 
   (uuid f07b4407-9283-4b53-a6ba-203b6b1b572a)
 
   (paper "A4")
 
   (title_block
-    (title "BUCube - Solar module Z")
-    (date "2021-06-01")
+    (title "BUCube - Solar module XY")
+    (date "2022-01-20")
     (rev "v1.0")
     (company "VUT")
     (comment 1 "Author: Petr Malaník")
@@ -41,14 +41,16 @@
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             (xy 2.032 -0.762)
           )
-          (stroke (width 0.508)) (fill (type none))
+          (stroke (width 0.508) (type default) (color 0 0 0 0))
+          (fill (type none))
         )
         (polyline
           (pts
             (xy -2.032 0.762)
             (xy 2.032 0.762)
           )
-          (stroke (width 0.508)) (fill (type none))
+          (stroke (width 0.508) (type default) (color 0 0 0 0))
+          (fill (type none))
         )
       )
       (symbol "C_1_1"
@@ -83,52 +85,60 @@
       )
       (symbol "Solar_Cell_0_1"
         (rectangle (start -2.032 1.778) (end 2.032 1.524)
-          (stroke (width 0)) (fill (type outline))
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type outline))
         )
         (rectangle (start -1.3208 1.1938) (end 1.27 0.6858)
-          (stroke (width 0)) (fill (type outline))
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type outline))
         )
         (polyline
           (pts
             (xy -2.032 2.286)
             (xy -3.556 3.81)
           )
-          (stroke (width 0)) (fill (type none))
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
         )
         (polyline
           (pts
             (xy -0.762 2.794)
             (xy -2.286 4.318)
           )
-          (stroke (width 0)) (fill (type none))
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
         )
         (polyline
           (pts
             (xy 0 0.762)
             (xy 0 0)
           )
-          (stroke (width 0)) (fill (type none))
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
         )
         (polyline
           (pts
             (xy 0 1.778)
             (xy 0 2.54)
           )
-          (stroke (width 0)) (fill (type none))
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
         )
         (polyline
           (pts
             (xy 0.254 2.667)
             (xy 1.27 2.667)
           )
-          (stroke (width 0.254)) (fill (type none))
+          (stroke (width 0.254) (type default) (color 0 0 0 0))
+          (fill (type none))
         )
         (polyline
           (pts
             (xy 0.762 3.175)
             (xy 0.762 2.159)
           )
-          (stroke (width 0.254)) (fill (type none))
+          (stroke (width 0.254) (type default) (color 0 0 0 0))
+          (fill (type none))
         )
         (polyline
           (pts
@@ -136,7 +146,8 @@
             (xy -2.032 2.286)
             (xy -2.794 2.286)
           )
-          (stroke (width 0)) (fill (type none))
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
         )
         (polyline
           (pts
@@ -144,7 +155,8 @@
             (xy -0.762 2.794)
             (xy -1.524 2.794)
           )
-          (stroke (width 0)) (fill (type none))
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
         )
       )
       (symbol "Solar_Cell_1_1"
@@ -179,7 +191,8 @@
       )
       (symbol "LM66100_0_1"
         (rectangle (start -6.35 5.08) (end 6.35 -5.08)
-          (stroke (width 0.254)) (fill (type background))
+          (stroke (width 0.254) (type default) (color 0 0 0 0))
+          (fill (type background))
         )
       )
       (symbol "LM66100_1_1"
@@ -192,7 +205,7 @@
           (number "2" (effects (font (size 1.27 1.27))))
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         (pin input line (at -8.89 -2.54 0) (length 2.54)
-          (name "~CE" (effects (font (size 1.27 1.27))))
+          (name "~{CE}" (effects (font (size 1.27 1.27))))
           (number "3" (effects (font (size 1.27 1.27))))
         )
         (pin output line (at 8.89 -2.54 180) (length 2.54)
@@ -234,7 +247,8 @@
             (xy -1.27 -1.27)
             (xy 0 -1.27)
           )
-          (stroke (width 0)) (fill (type none))
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
         )
       )
       (symbol "GND_1_1"
@@ -246,9 +260,49 @@
     )
   )
 
-  (junction (at 99.06 90.17) (diameter 1.016) (color 0 0 0 0))
-  (junction (at 128.27 90.17) (diameter 1.016) (color 0 0 0 0))
+  (junction (at 99.06 90.17) (diameter 1.016) (color 0 0 0 0)
+    (uuid 97998cb6-a494-40b7-8bbd-7df2c034b907)
+  )
+  (junction (at 128.27 90.17) (diameter 1.016) (color 0 0 0 0)
+    (uuid be4513c3-ecf4-4a57-a371-71a60e51a3f0)
+  )
 
+  (wire (pts (xy 99.06 99.06) (xy 99.06 100.33))
+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid 0a950af6-1312-414c-95d7-6621778b7135)
+  )
+  (wire (pts (xy 99.06 90.17) (xy 99.06 91.44))
+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid 14eb2a95-3c22-4d0c-9be0-b89a37d459f9)
+  )
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+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid 15b85bef-7550-45f9-be3b-c0a8c90f7200)
+  )
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+    (stroke (width 0) (type solid) (color 0 0 0 0))
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+  )
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+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid 887cbb09-1f15-43a8-acfc-207e7e7a34ba)
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+    (stroke (width 0) (type solid) (color 0 0 0 0))
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+  (wire (pts (xy 128.27 90.17) (xy 123.19 90.17))
+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid 887cbb09-1f15-43a8-acfc-207e7e7a34bc)
+  )
+  (wire (pts (xy 128.27 104.14) (xy 128.27 90.17))
+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid 887cbb09-1f15-43a8-acfc-207e7e7a34bd)
+  )
+  (wire (pts (xy 85.09 109.22) (xy 85.09 111.76))
+    (stroke (width 0) (type solid) (color 0 0 0 0))
+    (uuid 9d571d20-99ec-429e-a321-8982be849846)
+  )
   (wire (pts (xy 85.09 90.17) (xy 85.09 91.44))
     (stroke (width 0) (type solid) (color 0 0 0 0))
     (uuid a19d51ce-09ff-4763-8bd8-9f19b46659be)
@@ -257,29 +311,13 @@
     (stroke (width 0) (type solid) (color 0 0 0 0))
     (uuid d40f41ea-4180-45af-883f-0765adafcf20)
   )
-  (wire (pts (xy 85.09 99.06) (xy 85.09 101.6))
-    (stroke (width 0) (type solid) (color 0 0 0 0))
-    (uuid 15b85bef-7550-45f9-be3b-c0a8c90f7200)
-  )
-  (wire (pts (xy 99.06 90.17) (xy 99.06 91.44))
-    (stroke (width 0) (type solid) (color 0 0 0 0))
-    (uuid 14eb2a95-3c22-4d0c-9be0-b89a37d459f9)
-  )
   (wire (pts (xy 99.06 90.17) (xy 105.41 90.17))
     (stroke (width 0) (type solid) (color 0 0 0 0))
-    (uuid d40f41ea-4180-45af-883f-0765adafcf20)
+    (uuid d40f41ea-4180-45af-883f-0765adafcf21)
   )
-  (wire (pts (xy 99.06 99.06) (xy 99.06 100.33))
+  (wire (pts (xy 85.09 119.38) (xy 85.09 121.92))
     (stroke (width 0) (type solid) (color 0 0 0 0))
-    (uuid 0a950af6-1312-414c-95d7-6621778b7135)
-  )
-  (wire (pts (xy 105.41 95.25) (xy 105.41 104.14))
-    (stroke (width 0) (type solid) (color 0 0 0 0))
-    (uuid 887cbb09-1f15-43a8-acfc-207e7e7a34ba)
-  )
-  (wire (pts (xy 105.41 104.14) (xy 128.27 104.14))
-    (stroke (width 0) (type solid) (color 0 0 0 0))
-    (uuid 887cbb09-1f15-43a8-acfc-207e7e7a34ba)
+    (uuid f4a91bb3-c792-4909-b481-5f766c12d04f)
   )
   (wire (pts (xy 124.46 95.25) (xy 123.19 95.25))
     (stroke (width 0) (type solid) (color 0 0 0 0))
@@ -287,19 +325,7 @@
   )
   (wire (pts (xy 124.46 100.33) (xy 124.46 95.25))
     (stroke (width 0) (type solid) (color 0 0 0 0))
-    (uuid f6000d72-d9f2-447c-bfe6-6e5a597bebc9)
-  )
-  (wire (pts (xy 128.27 90.17) (xy 123.19 90.17))
-    (stroke (width 0) (type solid) (color 0 0 0 0))
-    (uuid 887cbb09-1f15-43a8-acfc-207e7e7a34ba)
-  )
-  (wire (pts (xy 128.27 90.17) (xy 134.62 90.17))
-    (stroke (width 0) (type solid) (color 0 0 0 0))
-    (uuid 7c5f2db0-21c3-45fc-bc73-ce414a62eb56)
-  )
-  (wire (pts (xy 128.27 104.14) (xy 128.27 90.17))
-    (stroke (width 0) (type solid) (color 0 0 0 0))
-    (uuid 887cbb09-1f15-43a8-acfc-207e7e7a34ba)
+    (uuid f6000d72-d9f2-447c-bfe6-6e5a597bebca)
   )
 
   (hierarchical_label "OUT" (shape input) (at 134.62 90.17 0)
@@ -307,46 +333,29 @@
     (uuid 69e3588f-e815-46f8-b7ce-6f605a0c9e5c)
   )
 
-  (symbol (lib_id "power:GND") (at 85.09 109.22 0)
-    (in_bom yes) (on_board yes) (fields_autoplaced)
-    (uuid 3b8f2ef0-559a-4bbb-b1b1-a793b965aa19)
-    (property "Reference" "#PWR0149" (id 0) (at 85.09 115.57 0)
+  (symbol (lib_id "Device:Solar_Cell") (at 85.09 106.68 0)
+    (in_bom yes) (on_board yes)
+    (uuid 0348ac21-372c-4d21-8b02-7758ba9a4bbd)
+    (property "Reference" "SC6" (id 0) (at 75.0571 104.6491 0)
+      (effects (font (size 1.27 1.27)) (justify left))
+    )
+    (property "Value" "SM141K04L" (id 1) (at 71.2471 106.9478 0)
+      (effects (font (size 1.27 1.27)) (justify left))
+    )
+    (property "Footprint" "TCY_solar:SM141K04LV" (id 2) (at 85.09 105.156 90)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "GND" (id 1) (at 85.09 113.5444 0)
+    (property "Datasheet" "~" (id 3) (at 85.09 105.156 90)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Footprint" "" (id 2) (at 85.09 109.22 0)
-      (effects (font (size 1.27 1.27)) hide)
-    )
-    (property "Datasheet" "" (id 3) (at 85.09 109.22 0)
-      (effects (font (size 1.27 1.27)) hide)
-    )
-    (pin "1" (uuid df9a530b-a451-4750-a2a9-ecdb9baf4a7b))
-  )
-
-  (symbol (lib_id "power:GND") (at 99.06 100.33 0)
-    (in_bom yes) (on_board yes) (fields_autoplaced)
-    (uuid 23967b27-4826-44d0-861c-6940554d5463)
-    (property "Reference" "#PWR0152" (id 0) (at 99.06 106.68 0)
-      (effects (font (size 1.27 1.27)) hide)
-    )
-    (property "Value" "GND" (id 1) (at 99.06 104.6544 0)
-      (effects (font (size 1.27 1.27)) hide)
-    )
-    (property "Footprint" "" (id 2) (at 99.06 100.33 0)
-      (effects (font (size 1.27 1.27)) hide)
-    )
-    (property "Datasheet" "" (id 3) (at 99.06 100.33 0)
-      (effects (font (size 1.27 1.27)) hide)
-    )
-    (pin "1" (uuid 69933c30-96f3-4687-a9c3-129175464b17))
+    (pin "1" (uuid ca2ccbf6-b2e5-4a9b-bc4d-684ed27bf55b))
+    (pin "2" (uuid e3b3ed30-1099-4d12-baa1-34038895f97e))
   )
 
   (symbol (lib_id "power:GND") (at 114.3 100.33 0)
     (in_bom yes) (on_board yes) (fields_autoplaced)
     (uuid 048d78ec-a044-483f-b782-0942fd867e33)
-    (property "Reference" "#PWR0151" (id 0) (at 114.3 106.68 0)
+    (property "Reference" "#PWR049" (id 0) (at 114.3 106.68 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (property "Value" "GND" (id 1) (at 114.3 104.6544 0)
@@ -361,10 +370,64 @@
     (pin "1" (uuid 4f591fec-8771-4414-afc9-222c56939f82))
   )
 
+  (symbol (lib_id "power:GND") (at 99.06 100.33 0)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid 23967b27-4826-44d0-861c-6940554d5463)
+    (property "Reference" "#PWR048" (id 0) (at 99.06 106.68 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Value" "GND" (id 1) (at 99.06 104.6544 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Footprint" "" (id 2) (at 99.06 100.33 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (id 3) (at 99.06 100.33 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 69933c30-96f3-4687-a9c3-129175464b17))
+  )
+
+  (symbol (lib_id "TCY_power_management:LM66100") (at 114.3 92.71 0)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid 30946d46-6cd3-49a1-94ab-464d3efaadf4)
+    (property "Reference" "U5" (id 0) (at 114.3 84.1968 0))
+    (property "Value" "LM66100" (id 1) (at 114.3 86.4955 0))
+    (property "Footprint" "Package_TO_SOT_SMD:SOT-363_SC-70-6" (id 2) (at 114.3 110.49 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "https://www.ti.com/lit/ds/symlink/lm66100.pdf?ts=1611216893994&ref_url=https%253A%252F%252Fwww.google.com%252F" (id 3) (at 114.3 114.3 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 21bc264f-1adc-4c29-87bb-ef8b761f4a60))
+    (pin "2" (uuid 92fb66b3-6ee5-4a82-8100-735a257bf132))
+    (pin "3" (uuid 463a84e0-995a-4228-8d71-08eb9fc534af))
+    (pin "5" (uuid c6158a69-4803-4018-b7e3-682381779d8c))
+    (pin "6" (uuid 50a2a776-0876-4d9e-aac5-91da2605abb4))
+  )
+
+  (symbol (lib_id "power:GND") (at 85.09 129.54 0)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid 3b8f2ef0-559a-4bbb-b1b1-a793b965aa19)
+    (property "Reference" "#PWR047" (id 0) (at 85.09 135.89 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Value" "GND" (id 1) (at 85.09 133.8644 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Footprint" "" (id 2) (at 85.09 129.54 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (id 3) (at 85.09 129.54 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid df9a530b-a451-4750-a2a9-ecdb9baf4a7b))
+  )
+
   (symbol (lib_id "power:GND") (at 124.46 100.33 0)
     (in_bom yes) (on_board yes) (fields_autoplaced)
     (uuid 855ea265-cf0f-467a-b7fb-994a04472f00)
-    (property "Reference" "#PWR0150" (id 0) (at 124.46 106.68 0)
+    (property "Reference" "#PWR050" (id 0) (at 124.46 106.68 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (property "Value" "GND" (id 1) (at 124.46 104.6544 0)
@@ -379,6 +442,44 @@
     (pin "1" (uuid 3aa8aad3-b63f-46d8-a9a4-e8af144a499f))
   )
 
+  (symbol (lib_id "Device:Solar_Cell") (at 85.09 116.84 0)
+    (in_bom yes) (on_board yes)
+    (uuid e00dc2dc-888b-476a-a6ba-087fab879145)
+    (property "Reference" "SC7" (id 0) (at 75.0571 114.8091 0)
+      (effects (font (size 1.27 1.27)) (justify left))
+    )
+    (property "Value" "SM141K04L" (id 1) (at 71.2471 117.1078 0)
+      (effects (font (size 1.27 1.27)) (justify left))
+    )
+    (property "Footprint" "TCY_solar:SM141K04LV" (id 2) (at 85.09 115.316 90)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "~" (id 3) (at 85.09 115.316 90)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 1db5ee0a-1faa-4892-be81-e1af9e9280d7))
+    (pin "2" (uuid 8488e29d-c288-41ef-98a7-272be9ef7cc5))
+  )
+
+  (symbol (lib_id "Device:Solar_Cell") (at 85.09 127 0)
+    (in_bom yes) (on_board yes)
+    (uuid e7ba0631-8a32-4cf8-b1e0-7389be80c395)
+    (property "Reference" "SC8" (id 0) (at 75.0571 124.9691 0)
+      (effects (font (size 1.27 1.27)) (justify left))
+    )
+    (property "Value" "SM141K04L" (id 1) (at 71.2471 127.2678 0)
+      (effects (font (size 1.27 1.27)) (justify left))
+    )
+    (property "Footprint" "TCY_solar:SM141K04LV" (id 2) (at 85.09 125.476 90)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "~" (id 3) (at 85.09 125.476 90)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 76df5a64-5382-4fe2-83b7-16168e290617))
+    (pin "2" (uuid 2cd22269-6904-465f-b343-92420b748c73))
+  )
+
   (symbol (lib_id "Device:C") (at 99.06 95.25 0)
     (in_bom yes) (on_board yes)
     (uuid ee08ea61-0c8e-460a-9877-62d6a6cd5886)
@@ -401,13 +502,13 @@
   (symbol (lib_id "Device:Solar_Cell") (at 85.09 96.52 0)
     (in_bom yes) (on_board yes)
     (uuid f5a0f36c-e5f8-4dd9-8887-885f56ec2a71)
-    (property "Reference" "SC7" (id 0) (at 75.0571 94.4891 0)
+    (property "Reference" "SC5" (id 0) (at 75.0571 94.4891 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
     (property "Value" "SM141K04L" (id 1) (at 71.2471 96.7878 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Footprint" "TCY_solar:SM141K04L" (id 2) (at 85.09 94.996 90)
+    (property "Footprint" "TCY_solar:SM141K04LV" (id 2) (at 85.09 94.996 90)
       (effects (font (size 1.27 1.27)) hide)
     )
     (property "Datasheet" "~" (id 3) (at 85.09 94.996 90)
@@ -416,41 +517,4 @@
     (pin "1" (uuid 3b156bda-6651-44cd-a108-773d3583d215))
     (pin "2" (uuid 4a941a7f-d1dd-482e-86bb-d6fbc2131969))
   )
-
-  (symbol (lib_id "Device:Solar_Cell") (at 85.09 106.68 0)
-    (in_bom yes) (on_board yes)
-    (uuid 0348ac21-372c-4d21-8b02-7758ba9a4bbd)
-    (property "Reference" "SC8" (id 0) (at 75.0571 104.6491 0)
-      (effects (font (size 1.27 1.27)) (justify left))
-    )
-    (property "Value" "SM141K04L" (id 1) (at 71.2471 106.9478 0)
-      (effects (font (size 1.27 1.27)) (justify left))
-    )
-    (property "Footprint" "TCY_solar:SM141K04L" (id 2) (at 85.09 105.156 90)
-      (effects (font (size 1.27 1.27)) hide)
-    )
-    (property "Datasheet" "~" (id 3) (at 85.09 105.156 90)
-      (effects (font (size 1.27 1.27)) hide)
-    )
-    (pin "1" (uuid ca2ccbf6-b2e5-4a9b-bc4d-684ed27bf55b))
-    (pin "2" (uuid e3b3ed30-1099-4d12-baa1-34038895f97e))
-  )
-
-  (symbol (lib_id "TCY_power_management:LM66100") (at 114.3 92.71 0)
-    (in_bom yes) (on_board yes) (fields_autoplaced)
-    (uuid 30946d46-6cd3-49a1-94ab-464d3efaadf4)
-    (property "Reference" "U7" (id 0) (at 114.3 84.1968 0))
-    (property "Value" "LM66100" (id 1) (at 114.3 86.4955 0))
-    (property "Footprint" "Package_TO_SOT_SMD:SOT-363_SC-70-6" (id 2) (at 114.3 110.49 0)
-      (effects (font (size 1.27 1.27)) hide)
-    )
-    (property "Datasheet" "https://www.ti.com/lit/ds/symlink/lm66100.pdf?ts=1611216893994&ref_url=https%253A%252F%252Fwww.google.com%252F" (id 3) (at 114.3 114.3 0)
-      (effects (font (size 1.27 1.27)) hide)
-    )
-    (pin "1" (uuid 21bc264f-1adc-4c29-87bb-ef8b761f4a60))
-    (pin "2" (uuid 92fb66b3-6ee5-4a82-8100-735a257bf132))
-    (pin "3" (uuid 463a84e0-995a-4228-8d71-08eb9fc534af))
-    (pin "5" (uuid c6158a69-4803-4018-b7e3-682381779d8c))
-    (pin "6" (uuid 50a2a776-0876-4d9e-aac5-91da2605abb4))
-  )
 )

modules/Solar_module_Z/Solar_module_Z.kicad_pro

@@ -33,9 +33,9 @@
         "other_text_thickness": 0.15,
         "other_text_upright": false,
         "pads": {
-          "drill": 0.762,
-          "height": 1.524,
-          "width": 1.524
+          "drill": 0.6,
+          "height": 1.0,
+          "width": 1.0
         },
         "silk_line_width": 0.15,
         "silk_text_italic": false,
@@ -62,7 +62,7 @@
       "rule_severities": {
         "annular_width": "error",
         "clearance": "error",
-        "copper_edge_clearance": "error",
+        "copper_edge_clearance": "warning",
         "courtyards_overlap": "error",
         "diff_pair_gap_out_of_range": "error",
         "diff_pair_uncoupled_length_too_long": "error",

modules/Solar_module_Z/Solar_module_Z.kicad_sch

@@ -7,7 +7,7 @@
   (title_block
     (title "BUCube - Solar module Z")
     (date "2021-06-01")
-    (rev "v1.0")
+    (rev "v1.1")
     (company "VUT")
     (comment 1 "Author: Petr Malaník")
   )

modules/Solar_module_Z/Solar_unit.kicad_sch

@@ -7,7 +7,7 @@
   (title_block
     (title "BUCube - Solar module Z")
     (date "2021-06-01")
-    (rev "v1.0")
+    (rev "v1.1")
     (company "VUT")
     (comment 1 "Author: Petr Malaník")
   )

modules/Solar_module_Z/fp-info-cache

@@ -1,4 +1,4 @@
-17046364675949326
+17059390668573890
 Battery
 BatteryHolder_Bulgin_BX0036_1xC
 Bulgin Battery Holder, BX0036, Battery Type C (https://www.bulgin.com/products/pub/media/bulgin/data/Battery_holders.pdf)
@@ -70133,6 +70133,27 @@ crystal oscillator quartz SMD SMT 5032
 4
 4
 TCY_IC
+DFN-3_1.2x1.2mm
+
+
+0
+3
+3
+TCY_IC
+DFN-8-1EP_4.5x4mm_P0.95mm_EP3.6x2.6mm
+
+
+0
+9
+9
+TCY_IC
+DFN-8-2EP_3x3mm_P0.65mm_EP2.0x1.2mm
+
+
+0
+8
+8
+TCY_IC
 MLF-4_1.2x1.6mm_P0.5_1EP_0.85x0.5mm
 
 
@@ -70167,6 +70188,13 @@ UTDFN-8-1EP_1.5x1.5mm_P0.4mm_EP0.8x1.45mm
 0
 9
 9
+TCY_IC
+VQFN-HR_29(34)_4x4mm_P0.4mm
+
+
+0
+33
+29
 TCY_buttons_switches
 EVQ-P7J01P
 Tactile Switch Right-angle
@@ -70294,6 +70322,20 @@ FPC_FH12-30S-0.5SVA_Male
 30
 30
 TCY_connectors
+Keystone_1049
+
+
+0
+4
+4
+TCY_connectors
+Keystone_1121
+
+
+0
+2
+2
+TCY_connectors
 LED_RGB_1210
 RGB LED 3.2x2.7mm http://www.avagotech.com/docs/AV02-0610EN
 LED 3227
@@ -70524,6 +70566,20 @@ TCY_QR_GITHUB_IO_6x6mm
 0
 0
 0
+TCY_oscillators
+CSP-4_1.5x0.8mm
+
+
+0
+4
+4
+TCY_oscillators
+ECS-TXO-3225
+
+
+0
+4
+4
 TCY_passives
 C_0603_1608Metric
 Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator
@@ -70606,7 +70662,7 @@ SM141K04L
 
 
 0
-2
+8
 2
 TCY_solar
 SM141K04LV

resources/Camera_driver/.gitignore

@@ -0,0 +1 @@
+build

resources/Camera_driver/App/butcube_imager.cpp

@@ -0,0 +1,18 @@
+#include "butcube_imager.hpp"
+
+int ButCube_imager::Transmit(vector<uint8_t> source){
+    for( auto &uart_output : uart_output_interfaces){
+        HAL_UART_Transmit(&uart_output, source.data(), source.size(), HAL_MAX_DELAY);
+        HAL_Delay(200);
+    }
+    return uart_output_interfaces.size() * source.size();
+}
+
+int ButCube_imager::Add_output(UART_HandleTypeDef uart_output){
+    uart_output_interfaces.emplace_back(uart_output);
+    return uart_output_interfaces.size();
+}
+
+void ButCube_imager::Camera_power(bool state){
+    HAL_GPIO_WritePin(GPIOA, CAMERA_EN_Pin, (GPIO_PinState)!state);
+}

resources/Camera_driver/App/butcube_imager.hpp

@@ -0,0 +1,59 @@
+/**
+ * @file OV2640.hpp
+ * @author Petr Malaník (TheColonelYoung(at)gmail(dot)com)
+ * @brief
+ * @version 0.1
+ * @date 11.09.2022
+ */
+
+#pragma once
+
+#include "stm32l4xx_hal.h"
+#include "main.h"
+
+#include <vector>
+
+using namespace std;
+typedef unsigned int uint;
+
+/**
+ * @brief Captures image data from camera, control power to camera and transmit data on selected interfaces
+ *          Currently is only UART interface supported
+ */
+class ButCube_imager
+{
+private:
+    /**
+     * @brief UART interfaces to which data will be exported, interfaces muse be configured in advance
+     */
+    vector<UART_HandleTypeDef> uart_output_interfaces;
+
+public:
+    /**
+     * @brief Construct a new ButCube_imager object
+     */
+    ButCube_imager() = default;
+
+    /**
+     * @brief Add UART output to list on which data are exported
+     *
+     * @param uart_output   UART output to which export data from camera
+     * @return int
+     */
+    int Add_output(UART_HandleTypeDef uart_output);
+
+    /**
+     * @brief Transmit data from source to selected interfaces
+     *
+     * @param source    Source of image data
+     * @return int      Count of bytes exported
+     */
+    int Transmit(vector<uint8_t> source);
+
+    /**
+     * @brief Enable or power to camera, controls load switch on camera power rail
+     *
+     * @param state true = Enabled, false = Disabled
+     */
+    void Camera_power(bool state);
+};

resources/Camera_driver/Camera_driver/OV2640.cpp

@@ -0,0 +1,54 @@
+#include "OV2640.hpp"
+
+void OV2640::Init(){
+    Sensor_write_register((uint8_t) 0xff, 0x01);
+    Sensor_write_register((uint8_t) 0x12, 0x80);
+
+    Sensor_write_register_bulk(OV2640_JPEG_INIT);
+    Sensor_write_register_bulk(OV2640_YUV422);
+    Sensor_write_register_bulk(OV2640_JPEG);
+
+    Sensor_write_register((uint8_t) 0xff, 0x01);
+    Sensor_write_register((uint8_t) 0x15, 0x00);
+}
+
+void OV2640::Init(const vector<Register_blob_8> &regs){
+    Init();
+
+    Sensor_write_register_bulk(regs);
+
+    // Setup camera, H-sync: High, V-sync:high, Sensor_delay: no Delay, FIFO_mode:FIFO enabled, power_mode:Low_power
+    ArduChip_write(0x03, 0b01010000);
+}
+
+void OV2640::Capture(){
+    ArduChip_write(0x04, 0x01); // Clear FIFO
+    ArduChip_write(0x04, 0x01);
+
+    HAL_Delay(1);
+
+    ArduChip_write(0x04, 0x02); // Start capture
+
+    HAL_Delay(1);
+
+    // wait for capture done
+    while (1) {
+        uint8_t regValue        = ArduChip_read(0x41);
+        uint8_t captureDoneMask = 0x8;
+        if (regValue & captureDoneMask) break;
+    }
+
+    HAL_Delay(1);
+
+    uint32_t image_size = ArduChip_FIFO_length();
+
+    image_data.resize(image_size);
+
+    ArduChip_start_DMA_transfer(image_size);
+
+    // while(SPI_handle.State != HAL_SPI_STATE_READY){;}
+    HAL_Delay(500); // delay to ensure full dma transmission
+
+    ArduChip_CS_disable();
+
+} // OV2640::Capture

resources/Camera_driver/Camera_driver/OV2640.hpp

@@ -0,0 +1,54 @@
+/**
+ * @file OV2640.hpp
+ * @author Petr Malaník (TheColonelYoung(at)gmail(dot)com)
+ * @brief
+ * @version 0.1
+ * @date 11.09.2022
+ */
+
+#pragma once
+
+#include "SPI_camera.hpp"
+#include "OV2640_regs.hpp"
+
+using namespace std;
+typedef unsigned int uint;
+
+/**
+ * @brief 2MP SPI based camera capable of JPEG compression, based on ArduChip
+ */
+class OV2640: protected SPI_camera
+{
+private:
+    /**
+     * @brief Initialize camera sensor for JPEG capture, without resolution settings
+     */
+    void Init() override final;
+
+public:
+    /**
+     * @brief Inherit constructor from parent class SPI_camera
+     */
+    using SPI_camera::SPI_camera;
+
+    /**
+     * @brief Initialize camera sensor for JPEG capture
+     *
+     * @param regs Requested resolution of camera
+     */
+    void Init(const vector<Register_blob_8> &regs);
+
+    /**
+     * @brief Initializes capture of image, waits for capture, transmit image into MCU memory
+     */
+    void Capture() override final;
+
+    /**
+     * @brief Return pointer to last captured image data
+     *
+     * @return vector<uint8_t>  Pointer to last captured image data
+     */
+    vector<uint8_t> Image_data(){ return image_data; };
+};
+
+

resources/Camera_driver/Camera_driver/OV2640_regs.cpp

@@ -0,0 +1 @@
+#include "OV2640_regs.hpp"

resources/Camera_driver/Camera_driver/SPI_camera.cpp

@@ -0,0 +1,107 @@
+#include "SPI_camera.hpp"
+
+SPI_camera::SPI_camera(I2C_HandleTypeDef I2C_handle, uint8_t I2C_address, SPI_HandleTypeDef SPI_handle, Chip_select_pin SPI_CS) : I2C_handle(I2C_handle), I2C_address(
+        I2C_address), SPI_handle(SPI_handle), SPI_CS(SPI_CS){ }
+
+int SPI_camera::Sensor_write_register(uint8_t address, uint8_t data){
+    return Sensor_write_register(Register_blob_8{ address, data });
+}
+
+int SPI_camera::Sensor_write_register(uint16_t address, uint8_t data){
+    return Sensor_write_register(Register_blob_16{ address, data });
+}
+
+int SPI_camera::Sensor_write_register(Register_blob_8 reg){
+    HAL_StatusTypeDef ret;
+
+    uint8_t buf[2];
+    buf[0] = reg.address;
+    buf[1] = reg.data;
+    ret    = HAL_I2C_Master_Transmit(&I2C_handle, I2C_address, buf, 2, HAL_MAX_DELAY);
+
+    if (ret == HAL_OK) return (1);
+
+    return (0);
+}
+
+int SPI_camera::Sensor_write_register(Register_blob_16 reg){
+    HAL_StatusTypeDef ret;
+    uint8_t buf[3];
+
+    buf[0] = reg.address >> 8;
+    buf[1] = reg.address & 0x00ff;
+    buf[2] = reg.data;
+    ret    = HAL_I2C_Master_Transmit(&I2C_handle, I2C_address, buf, 3, HAL_MAX_DELAY);
+
+    if (ret == HAL_OK) return (1);
+
+    return (0);
+}
+
+void SPI_camera::Sensor_write_register_bulk(vector<Register_blob_8> regs){
+    for (unsigned int i = 0; i < regs.size(); i++) {
+        Register_blob_8 &reg = regs[i];
+        if ( (reg.address == 0xff) & (reg.data == 0xff) ) {
+            break;
+        } else {
+            Sensor_write_register(regs[i]);
+        }
+    }
+}
+
+void SPI_camera::Sensor_write_register_bulk(vector<Register_blob_16> regs){ }
+
+int SPI_camera::ArduChip_write(uint8_t addr, uint8_t data){
+    HAL_StatusTypeDef ret;
+
+    uint8_t addr_write = addr | 0x80;
+
+    ArduChip_CS_enable();
+
+    ret = HAL_SPI_Transmit(&SPI_handle, (uint8_t *) &addr_write, 1, HAL_MAX_DELAY);
+    if (ret != HAL_OK) {
+        return ret;
+    }
+
+    ret = HAL_SPI_Transmit(&SPI_handle, (uint8_t *) &data, 1, HAL_MAX_DELAY);
+    if (ret != HAL_OK) {
+        return ret;
+    }
+
+    ArduChip_CS_disable();
+    return 0;
+}
+
+int SPI_camera::ArduChip_read(uint8_t address){
+    uint8_t addrMasked = address & 0x7F;
+    uint8_t empty      = 0x00;
+    uint8_t ret;
+
+    ArduChip_CS_enable();
+    HAL_SPI_TransmitReceive(&SPI_handle, &addrMasked, &ret, 1, HAL_MAX_DELAY);
+    HAL_SPI_TransmitReceive(&SPI_handle, &empty, &ret, 1, HAL_MAX_DELAY);
+    ArduChip_CS_disable();
+
+    return ret;
+}
+
+int SPI_camera::ArduChip_FIFO_length(){
+    uint32_t len1, len2, len3, len = 0;
+    len1 = ArduChip_read(0x42);
+    len2 = ArduChip_read(0x43);
+    len3 = ArduChip_read(0x44) & 0x7f;
+    len  = ((len3 << 16) | (len2 << 8) | len1) & 0x07fffff;
+    return len;
+}
+
+void SPI_camera::ArduChip_start_burst_read(){
+    uint8_t BURST_FIFO_READ = 0x3c;
+    uint8_t empty = 0x00;
+    HAL_SPI_TransmitReceive(&SPI_handle, &BURST_FIFO_READ, &empty, 1, HAL_MAX_DELAY);
+}
+
+void SPI_camera::ArduChip_start_DMA_transfer(uint size){
+    ArduChip_CS_enable();
+    ArduChip_start_burst_read();
+    HAL_SPI_Receive_DMA(&SPI_handle, image_data.data(), size);
+}

resources/Camera_driver/Camera_driver/SPI_camera.hpp

@@ -0,0 +1,201 @@
+/**
+ * @file SPI_camera.hpp
+ * @author Petr Malaník (TheColonelYoung(at)gmail(dot)com)
+ * @brief
+ * @version 0.1
+ * @date 11.09.2022
+ */
+
+#pragma once
+
+#include "stm32l4xx_hal.h"
+
+#include <vector>
+#include <array>
+#include <memory>
+
+using namespace std;
+typedef unsigned int uint;
+
+/**
+ * @brief Class representing SPI cameras based on Arduchip solution
+ *          Currently is only supported OV2640
+ */
+class SPI_camera
+{
+public:
+    /**
+     * @brief Describes GPIO which serves as SPI chip select pin
+     */
+    struct Chip_select_pin {
+        GPIO_TypeDef *port;
+        uint16_t      pin;
+    };
+
+    /**
+     * @brief Represents address and data of sensor settings, 8bit address, 8 bit data for example for OV2640 sensor
+     */
+    struct Register_blob_8 {
+        uint8_t address;
+        uint8_t data;
+    };
+
+    /**
+     * @brief Represents address and data of sensor settings, 16bit address, 8 bit data for example for OV5642 sensor
+     */
+    struct Register_blob_16 {
+        uint16_t address;
+        uint8_t  data;
+    };
+
+protected:
+    /**
+     * @brief HAL handle of I2C which is connected to image sensor
+     */
+    I2C_HandleTypeDef I2C_handle;
+
+    /**
+     * @brief I2C address of sensor
+     *          Common values: 0x60 for OV2640, 0x78 for OV5642
+     */
+    uint8_t I2C_address = 0;
+
+    /**
+     * @brief HAL handle of SPI to which is ArduChip connected
+     */
+    SPI_HandleTypeDef SPI_handle;
+
+    /**
+     * @brief GPIO description which serves as SPI Chip select
+     */
+    Chip_select_pin SPI_CS;
+
+    /**
+     * @brief Raw image data transmitted from ArduChip via SPI to MCu memory
+     */
+    vector<uint8_t> image_data;
+
+public:
+    /**
+     * @brief Construct a new SPI camera object
+     *
+     * @param I2C_handle    HAL handle of I2C which is connected to image sensor
+     * @param I2C_address   I2C address of sensor, Common values: 0x60 for OV2640, 0x78 for OV5642
+     * @param SPI_handle    HAL handle of SPI to which is ArduChip connected
+     * @param SPI_CS        GPIO description which serves as SPI Chip select
+     */
+    SPI_camera(I2C_HandleTypeDef I2C_handle, uint8_t I2C_address, SPI_HandleTypeDef SPI_handle, Chip_select_pin SPI_CS);
+
+    /**
+     * @brief Virtual function for camera initialization, depends on camera model
+     */
+    virtual void Init() = 0;
+
+    /**
+     * @brief Virtual function for image capture, depends on camera model
+     */
+    virtual void Capture() = 0;
+
+protected:
+
+    /**
+     * @brief   Write 8-bit data to 8-bit address in image sensor via I2C, used for example in OV2640
+     *
+     * @param address   Address (8-bit) to write
+     * @param data      Data (8-bit) to write
+     * @return int      HAL status
+     */
+    int Sensor_write_register(uint8_t address, uint8_t data);
+
+    /**
+     * @brief   Write 8-bit data to 16-bit address in image sensor via I2C, used for example in OV5642
+     *
+     * @param address   Address (16-bit) to write
+     * @param data      Data (8-bit) to write
+     * @return int      HAL status
+     */
+    int Sensor_write_register(uint16_t address, uint8_t data);
+
+    /**
+     * @brief   Write register representation in structure (8-bit address, 8-bit data) into image sensor via I2C
+     *              used for example in OV2640
+     *
+     * @param reg   Register represented in structure (8-bit address, 8-bit data), used for example in OV2640
+     * @return int  HAL status
+     */
+    int Sensor_write_register(Register_blob_8 reg);
+
+    /**
+     * @brief   Write register representation in structure (16-bit address, 8-bit data) into image sensor via I2C
+     *              used for example in OV5642
+     *
+     * @param reg   Register represented in structure (16-bit address, 8-bit data), used for example in OV5642
+     * @return int  HAL status
+     */
+    int Sensor_write_register(Register_blob_16 reg);
+
+    /**
+     * @brief   Write vector of register settings (8-bit address, 8-bit data) into image sensor in bulk
+      *              used for example in OV2640
+     *
+     * @param regs  vector containing register settings (8-bit address, 8-bit data)
+     */
+    void Sensor_write_register_bulk(vector<Register_blob_16> regs);
+
+    /**
+     * @brief   Write vector of register settings (16-bit address, 8-bit data) into image sensor in bulk
+     *              used for example in OV5642
+     *
+     * @param regs  vector containing register settings (16-bit address, 8-bit data), used for example in OV5642
+     */
+    void Sensor_write_register_bulk(vector<Register_blob_8> regs);
+
+    /**
+     * @brief Write data (8-bit) into register address (8-bit) of ArduChip via SPI
+     *
+     * @param addr  Address (8-bit) to write
+     * @param data  Data (8-bit) to write
+     * @return int  HAL status
+     */
+    int ArduChip_write(uint8_t addr, uint8_t data);
+
+    /**
+     * @brief Read data (8-bit) from register address (8-bit) of ArduChip via SPI
+     *
+     * @param address Address (8-bit) from which read
+     * @return int  HAL status
+     */
+    int ArduChip_read(uint8_t address);
+
+    /**
+     * @brief Calculates size of FIFO which is used for image data inside ArduChip
+     *              Performs communication via SPI with ArduChip
+     *
+     * @return int  Count of bytes in FIFO of ArduChip
+     */
+    int ArduChip_FIFO_length();
+
+    /**
+     * @brief   Initialize Burst read of FIFO containing image data via SPI from ArduChip
+     *              Must be followed by DMA request and read, after readout is complete CS signal must be disabled
+     */
+    void ArduChip_start_burst_read();
+
+    /**
+     * @brief   Initialize DMA transfer of image data from ArduChip FIFO via SPI
+     *              Burst read operation must be setup before,  after readout is complete CS signal must be disabled
+     *
+     * @param size Amount of bytes to read
+     */
+    void ArduChip_start_DMA_transfer(uint size);
+
+    /**
+     * @brief Enable communication with ArduChip via SPI, CS signal is active low
+     */
+    void ArduChip_CS_enable(){ HAL_GPIO_WritePin(SPI_CS.port, SPI_CS.pin, GPIO_PIN_RESET); };
+
+    /**
+     * @brief Disables communication with ArduChip via SPI, CS signal is active low
+     */
+    void ArduChip_CS_disable(){ HAL_GPIO_WritePin(SPI_CS.port, SPI_CS.pin, GPIO_PIN_SET); };
+};

resources/Camera_driver/Drivers/CMSIS/Core/Include/cmsis_armcc.h

@@ -0,0 +1,894 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version  V5.1.0
+ * @date     08. May 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+  #define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+  #define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+  #define __ARM_ARCH_7EM__          1
+#endif
+
+  /* __ARM_ARCH_8M_BASE__  not applicable */
+  /* __ARM_ARCH_8M_MAIN__  not applicable */
+
+/* CMSIS compiler control DSP macros */
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __ARM_FEATURE_DSP         1
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   static __forceinline
+#endif           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         __packed union
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER()                   __memory_changed()
+#endif
+
+/* #########################  Startup and Lowlevel Init  ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section("RESET")))
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+                  
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return result;
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */

resources/Camera_driver/Drivers/CMSIS/Core/Include/cmsis_compiler.h

@@ -0,0 +1,283 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.1.0
+ * @date     09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+  #include "cmsis_armclang_ltm.h"
+
+  /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

resources/Camera_driver/Drivers/CMSIS/Core/Include/cmsis_iccarm.h

@@ -0,0 +1,964 @@
+/**************************************************************************//**
+ * @file     cmsis_iccarm.h
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version  V5.1.0
+ * @date     08. May 2019
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2019 IAR Systems
+// Copyright (c) 2017-2019 Arm Limited. All rights reserved. 
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+  #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+  #define __ICCARM_V8 1
+#else
+  #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+  #if __ICCARM_V8
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #elif (__VER__ >= 7080000)
+    /* Needs IAR language extensions */
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #else
+    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+    #if __ARM_ARCH == 6
+      #define __ARM_ARCH_6M__ 1
+    #elif __ARM_ARCH == 7
+      #if __ARM_FEATURE_DSP
+        #define __ARM_ARCH_7EM__ 1
+      #else
+        #define __ARM_ARCH_7M__ 1
+      #endif
+    #endif /* __ARM_ARCH */
+  #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+    #define __ARM_ARCH_6M__ 1
+  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+    #define __ARM_ARCH_7M__ 1
+  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+    #define __ARM_ARCH_7EM__  1
+  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #else
+    #error "Unknown target."
+  #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+  #define __IAR_M0_FAMILY  1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+  #define __IAR_M0_FAMILY  1
+#else
+  #define __IAR_M0_FAMILY  0
+#endif
+
+
+#ifndef __ASM
+  #define __ASM __asm
+#endif
+
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+#ifndef __INLINE
+  #define __INLINE inline
+#endif
+
+#ifndef   __NO_RETURN
+  #if __ICCARM_V8
+    #define __NO_RETURN __attribute__((__noreturn__))
+  #else
+    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+  #endif
+#endif
+
+#ifndef   __PACKED
+  #if __ICCARM_V8
+    #define __PACKED __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED __packed
+  #endif
+#endif
+
+#ifndef   __PACKED_STRUCT
+  #if __ICCARM_V8
+    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_STRUCT __packed struct
+  #endif
+#endif
+
+#ifndef   __PACKED_UNION
+  #if __ICCARM_V8
+    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_UNION __packed union
+  #endif
+#endif
+
+#ifndef   __RESTRICT
+  #if __ICCARM_V8
+    #define __RESTRICT            __restrict
+  #else
+    /* Needs IAR language extensions */
+    #define __RESTRICT            restrict
+  #endif
+#endif
+
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE       static inline
+#endif
+
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE         _Pragma("inline=forced")
+#endif
+
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+  return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+  *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+  return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+  *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32   /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct  __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef   __USED
+  #if __ICCARM_V8
+    #define __USED __attribute__((used))
+  #else
+    #define __USED _Pragma("__root")
+  #endif
+#endif
+
+#ifndef   __WEAK
+  #if __ICCARM_V8
+    #define __WEAK __attribute__((weak))
+  #else
+    #define __WEAK _Pragma("__weak")
+  #endif
+#endif
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __iar_program_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              CSTACK$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             CSTACK$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __vector_table
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  @".intvec"
+#endif
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+  #define __ICCARM_INTRINSICS_VERSION__  0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+  #if defined(__CLZ)
+    #undef __CLZ
+  #endif
+  #if defined(__REVSH)
+    #undef __REVSH
+  #endif
+  #if defined(__RBIT)
+    #undef __RBIT
+  #endif
+  #if defined(__SSAT)
+    #undef __SSAT
+  #endif
+  #if defined(__USAT)
+    #undef __USAT
+  #endif
+
+  #include "iccarm_builtin.h"
+
+  #define __disable_fault_irq __iar_builtin_disable_fiq
+  #define __disable_irq       __iar_builtin_disable_interrupt
+  #define __enable_fault_irq  __iar_builtin_enable_fiq
+  #define __enable_irq        __iar_builtin_enable_interrupt
+  #define __arm_rsr           __iar_builtin_rsr
+  #define __arm_wsr           __iar_builtin_wsr
+
+
+  #define __get_APSR()                (__arm_rsr("APSR"))
+  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
+  #define __get_CONTROL()             (__arm_rsr("CONTROL"))
+  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
+
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
+    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
+  #else
+    #define __get_FPSCR()             ( 0 )
+    #define __set_FPSCR(VALUE)        ((void)VALUE)
+  #endif
+
+  #define __get_IPSR()                (__arm_rsr("IPSR"))
+  #define __get_MSP()                 (__arm_rsr("MSP"))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __get_MSPLIM()            (0U)
+  #else
+    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))
+  #endif
+  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
+  #define __get_PSP()                 (__arm_rsr("PSP"))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __get_PSPLIM()            (0U)
+  #else
+    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))
+  #endif
+
+  #define __get_xPSR()                (__arm_rsr("xPSR"))
+
+  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
+  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
+  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
+  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
+  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __set_MSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))
+  #endif
+  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
+  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __set_PSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))
+  #endif
+
+  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
+  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
+  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
+  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
+  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
+  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
+  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
+  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
+  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
+  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
+  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
+  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
+  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
+  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __TZ_get_PSPLIM_NS()      (0U)
+    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+  #else
+    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
+    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #endif
+
+  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
+  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+  #define __NOP     __iar_builtin_no_operation
+
+  #define __CLZ     __iar_builtin_CLZ
+  #define __CLREX   __iar_builtin_CLREX
+
+  #define __DMB     __iar_builtin_DMB
+  #define __DSB     __iar_builtin_DSB
+  #define __ISB     __iar_builtin_ISB
+
+  #define __LDREXB  __iar_builtin_LDREXB
+  #define __LDREXH  __iar_builtin_LDREXH
+  #define __LDREXW  __iar_builtin_LDREX
+
+  #define __RBIT    __iar_builtin_RBIT
+  #define __REV     __iar_builtin_REV
+  #define __REV16   __iar_builtin_REV16
+
+  __IAR_FT int16_t __REVSH(int16_t val)
+  {
+    return (int16_t) __iar_builtin_REVSH(val);
+  }
+
+  #define __ROR     __iar_builtin_ROR
+  #define __RRX     __iar_builtin_RRX
+
+  #define __SEV     __iar_builtin_SEV
+
+  #if !__IAR_M0_FAMILY
+    #define __SSAT    __iar_builtin_SSAT
+  #endif
+
+  #define __STREXB  __iar_builtin_STREXB
+  #define __STREXH  __iar_builtin_STREXH
+  #define __STREXW  __iar_builtin_STREX
+
+  #if !__IAR_M0_FAMILY
+    #define __USAT    __iar_builtin_USAT
+  #endif
+
+  #define __WFE     __iar_builtin_WFE
+  #define __WFI     __iar_builtin_WFI
+
+  #if __ARM_MEDIA__
+    #define __SADD8   __iar_builtin_SADD8
+    #define __QADD8   __iar_builtin_QADD8
+    #define __SHADD8  __iar_builtin_SHADD8
+    #define __UADD8   __iar_builtin_UADD8
+    #define __UQADD8  __iar_builtin_UQADD8
+    #define __UHADD8  __iar_builtin_UHADD8
+    #define __SSUB8   __iar_builtin_SSUB8
+    #define __QSUB8   __iar_builtin_QSUB8
+    #define __SHSUB8  __iar_builtin_SHSUB8
+    #define __USUB8   __iar_builtin_USUB8
+    #define __UQSUB8  __iar_builtin_UQSUB8
+    #define __UHSUB8  __iar_builtin_UHSUB8
+    #define __SADD16  __iar_builtin_SADD16
+    #define __QADD16  __iar_builtin_QADD16
+    #define __SHADD16 __iar_builtin_SHADD16
+    #define __UADD16  __iar_builtin_UADD16
+    #define __UQADD16 __iar_builtin_UQADD16
+    #define __UHADD16 __iar_builtin_UHADD16
+    #define __SSUB16  __iar_builtin_SSUB16
+    #define __QSUB16  __iar_builtin_QSUB16
+    #define __SHSUB16 __iar_builtin_SHSUB16
+    #define __USUB16  __iar_builtin_USUB16
+    #define __UQSUB16 __iar_builtin_UQSUB16
+    #define __UHSUB16 __iar_builtin_UHSUB16
+    #define __SASX    __iar_builtin_SASX
+    #define __QASX    __iar_builtin_QASX
+    #define __SHASX   __iar_builtin_SHASX
+    #define __UASX    __iar_builtin_UASX
+    #define __UQASX   __iar_builtin_UQASX
+    #define __UHASX   __iar_builtin_UHASX
+    #define __SSAX    __iar_builtin_SSAX
+    #define __QSAX    __iar_builtin_QSAX
+    #define __SHSAX   __iar_builtin_SHSAX
+    #define __USAX    __iar_builtin_USAX
+    #define __UQSAX   __iar_builtin_UQSAX
+    #define __UHSAX   __iar_builtin_UHSAX
+    #define __USAD8   __iar_builtin_USAD8
+    #define __USADA8  __iar_builtin_USADA8
+    #define __SSAT16  __iar_builtin_SSAT16
+    #define __USAT16  __iar_builtin_USAT16
+    #define __UXTB16  __iar_builtin_UXTB16
+    #define __UXTAB16 __iar_builtin_UXTAB16
+    #define __SXTB16  __iar_builtin_SXTB16
+    #define __SXTAB16 __iar_builtin_SXTAB16
+    #define __SMUAD   __iar_builtin_SMUAD
+    #define __SMUADX  __iar_builtin_SMUADX
+    #define __SMMLA   __iar_builtin_SMMLA
+    #define __SMLAD   __iar_builtin_SMLAD
+    #define __SMLADX  __iar_builtin_SMLADX
+    #define __SMLALD  __iar_builtin_SMLALD
+    #define __SMLALDX __iar_builtin_SMLALDX
+    #define __SMUSD   __iar_builtin_SMUSD
+    #define __SMUSDX  __iar_builtin_SMUSDX
+    #define __SMLSD   __iar_builtin_SMLSD
+    #define __SMLSDX  __iar_builtin_SMLSDX
+    #define __SMLSLD  __iar_builtin_SMLSLD
+    #define __SMLSLDX __iar_builtin_SMLSLDX
+    #define __SEL     __iar_builtin_SEL
+    #define __QADD    __iar_builtin_QADD
+    #define __QSUB    __iar_builtin_QSUB
+    #define __PKHBT   __iar_builtin_PKHBT
+    #define __PKHTB   __iar_builtin_PKHTB
+  #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #define __CLZ  __cmsis_iar_clz_not_active
+    #define __SSAT __cmsis_iar_ssat_not_active
+    #define __USAT __cmsis_iar_usat_not_active
+    #define __RBIT __cmsis_iar_rbit_not_active
+    #define __get_APSR  __cmsis_iar_get_APSR_not_active
+  #endif
+
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+  #endif
+
+  #ifdef __INTRINSICS_INCLUDED
+  #error intrinsics.h is already included previously!
+  #endif
+
+  #include <intrinsics.h>
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #undef __CLZ
+    #undef __SSAT
+    #undef __USAT
+    #undef __RBIT
+    #undef __get_APSR
+
+    __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+    {
+      if (data == 0U) { return 32U; }
+
+      uint32_t count = 0U;
+      uint32_t mask = 0x80000000U;
+
+      while ((data & mask) == 0U)
+      {
+        count += 1U;
+        mask = mask >> 1U;
+      }
+      return count;
+    }
+
+    __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+    {
+      uint8_t sc = 31U;
+      uint32_t r = v;
+      for (v >>= 1U; v; v >>= 1U)
+      {
+        r <<= 1U;
+        r |= v & 1U;
+        sc--;
+      }
+      return (r << sc);
+    }
+
+    __STATIC_INLINE  uint32_t __get_APSR(void)
+    {
+      uint32_t res;
+      __asm("MRS      %0,APSR" : "=r" (res));
+      return res;
+    }
+
+  #endif
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #undef __get_FPSCR
+    #undef __set_FPSCR
+    #define __get_FPSCR()       (0)
+    #define __set_FPSCR(VALUE)  ((void)VALUE)
+  #endif
+
+  #pragma diag_suppress=Pe940
+  #pragma diag_suppress=Pe177
+
+  #define __enable_irq    __enable_interrupt
+  #define __disable_irq   __disable_interrupt
+  #define __NOP           __no_operation
+
+  #define __get_xPSR      __get_PSR
+
+  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+    {
+      return __LDREX((unsigned long *)ptr);
+    }
+
+    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+    {
+      return __STREX(value, (unsigned long *)ptr);
+    }
+  #endif
+
+
+  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+  #if (__CORTEX_M >= 0x03)
+
+    __IAR_FT uint32_t __RRX(uint32_t value)
+    {
+      uint32_t result;
+      __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
+      return(result);
+    }
+
+    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));
+    }
+
+
+    #define __enable_fault_irq  __enable_fiq
+    #define __disable_fault_irq __disable_fiq
+
+
+  #endif /* (__CORTEX_M >= 0x03) */
+
+  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+  {
+    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+  }
+
+  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+   __IAR_FT uint32_t __get_MSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_MSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __get_PSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_PSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
+    {
+      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_SP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,SP_NS" : "=r" (res));
+      return res;
+    }
+    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      SP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));
+    }
+
+  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+  {
+    if ((sat >= 1U) && (sat <= 32U))
+    {
+      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+      const int32_t min = -1 - max ;
+      if (val > max)
+      {
+        return max;
+      }
+      else if (val < min)
+      {
+        return min;
+      }
+    }
+    return val;
+  }
+
+  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+  {
+    if (sat <= 31U)
+    {
+      const uint32_t max = ((1U << sat) - 1U);
+      if (val > (int32_t)max)
+      {
+        return max;
+      }
+      else if (val < 0)
+      {
+        return 0U;
+      }
+    }
+    return (uint32_t)val;
+  }
+#endif
+
+#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+  {
+    __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+  {
+    __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+  {
+    __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+  }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+
+  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+  {
+    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+  {
+    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+  {
+    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */

resources/Camera_driver/Drivers/CMSIS/Core/Include/cmsis_version.h

@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.3
+ * @date     24. June 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 3U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

resources/Camera_driver/Drivers/CMSIS/Core/Include/core_cm0.h

@@ -0,0 +1,952 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V5.0.6
+ * @date     13. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M0
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_FP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000U
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RESERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t vectors = 0x0U;
+  (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
+  /* ARM Application Note 321 states that the M0 does not require the architectural barrier */
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t vectors = 0x0U;
+  return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

resources/Camera_driver/Drivers/CMSIS/Core/Include/core_cm1.h

@@ -0,0 +1,979 @@
+/**************************************************************************//**
+ * @file     core_cm1.h
+ * @brief    CMSIS Cortex-M1 Core Peripheral Access Layer Header File
+ * @version  V1.0.1
+ * @date     12. November 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM1_H_GENERIC
+#define __CORE_CM1_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M1
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM1 definitions */
+#define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM1_CMSIS_VERSION       ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM1_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (1U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_FP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM1_H_DEPENDANT
+#define __CORE_CM1_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM1_REV
+    #define __CM1_REV               0x0100U
+    #warning "__CM1_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M1 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_ITCMUAEN_Pos            4U                                        /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMUAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)         /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
+
+#define SCnSCB_ACTLR_ITCMLAEN_Pos            3U                                        /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMLAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)         /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M1 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M1 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+  /* ARM Application Note 321 states that the M1 does not require the architectural barrier */
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

resources/Camera_driver/Drivers/CMSIS/Core/Include/mpu_armv7.h

@@ -0,0 +1,272 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.1.0
+ * @date     08. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+* 
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/  
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
+  ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                  | \
+   (((IsShareable)  << MPU_RASR_S_Pos)   & MPU_RASR_S_Msk)                    | \
+   (((IsCacheable)  << MPU_RASR_C_Pos)   & MPU_RASR_C_Msk)                    | \
+   (((IsBufferable) << MPU_RASR_B_Pos)   & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)    \
+  ((((DisableExec)      << MPU_RASR_XN_Pos)   & MPU_RASR_XN_Msk)                                  | \
+   (((AccessPermission) << MPU_RASR_AP_Pos)   & MPU_RASR_AP_Msk)                                  | \
+   (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
+   (((SubRegionDisable) << MPU_RASR_SRD_Pos)  & MPU_RASR_SRD_Msk)                                 | \
+   (((Size)             << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk)                                | \
+   (((MPU_RASR_ENABLE_Msk))))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+*  - TEX: 000b
+*  - Shareable
+*  - Non-cacheable
+*  - Non-bufferable
+*/ 
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+*  - TEX: 000b (if shareable) or 010b (if non-shareable)
+*  - Shareable or non-shareable
+*  - Non-cacheable
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+*  - TEX: 1BBb (reflecting outer cacheability rules)
+*  - Shareable or non-shareable
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif

resources/Camera_driver/Drivers/CMSIS/Core/Include/mpu_armv8.h

@@ -0,0 +1,346 @@
+/******************************************************************************
+ * @file     mpu_armv8.h
+ * @brief    CMSIS MPU API for Armv8-M and Armv8.1-M MPU
+ * @version  V5.1.0
+ * @date     08. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE                           ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable  */
+#define ARM_MPU_SH_NON   (0U)
+
+/** \brief Normal memory outer shareable  */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable  */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+  ((BASE & MPU_RBAR_BASE_Msk) | \
+  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+
+#if defined(MPU_RLAR_PXN_Pos)
+  
+/** \brief Region Limit Address Register with PXN value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
+  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+  ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
+  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+  
+#endif
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR;                   /*!< Region Base Address Register value */
+  uint32_t RLAR;                   /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+  const uint8_t reg = idx / 4U;
+  const uint32_t pos = ((idx % 4U) * 8U);
+  const uint32_t mask = 0xFFU << pos;
+  
+  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+    return; // invalid index
+  }
+  
+  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+  mpu->RNR = rnr;
+  mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{  
+  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  mpu->RNR = rnr;
+  mpu->RBAR = rbar;
+  mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  if (cnt == 1U) {
+    mpu->RNR = rnr;
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+  } else {
+    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
+    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+    
+    mpu->RNR = rnrBase;
+    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+      ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      table += c;
+      cnt -= c;
+      rnrOffset = 0U;
+      rnrBase += MPU_TYPE_RALIASES;
+      mpu->RNR = rnrBase;
+    }
+    
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+

resources/Camera_driver/Drivers/CMSIS/Core/Include/tz_context.h

@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include <stdint.h>
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H

resources/Camera_driver/Drivers/CMSIS/Core/Template/ARMv8-M/main_s.c

@@ -0,0 +1,58 @@
+/******************************************************************************
+ * @file     main_s.c
+ * @brief    Code template for secure main function
+ * @version  V1.1.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Use CMSE intrinsics */
+#include <arm_cmse.h>
+ 
+#include "RTE_Components.h"
+#include CMSIS_device_header
+ 
+/* TZ_START_NS: Start address of non-secure application */
+#ifndef TZ_START_NS
+#define TZ_START_NS (0x200000U)
+#endif
+ 
+/* typedef for non-secure callback functions */
+typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call));
+ 
+/* Secure main() */
+int main(void) {
+  funcptr_void NonSecure_ResetHandler;
+ 
+  /* Add user setup code for secure part here*/
+ 
+  /* Set non-secure main stack (MSP_NS) */
+  __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS)));
+ 
+  /* Get non-secure reset handler */
+  NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U)));
+ 
+  /* Start non-secure state software application */
+  NonSecure_ResetHandler();
+ 
+  /* Non-secure software does not return, this code is not executed */
+  while (1) {
+    __NOP();
+  }
+}

resources/Camera_driver/Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.c

@@ -0,0 +1,200 @@
+/******************************************************************************
+ * @file     tz_context.c
+ * @brief    Context Management for Armv8-M TrustZone - Sample implementation
+ * @version  V1.1.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2016-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+#include "tz_context.h"
+
+/// Number of process slots (threads may call secure library code)
+#ifndef TZ_PROCESS_STACK_SLOTS
+#define TZ_PROCESS_STACK_SLOTS     8U
+#endif
+
+/// Stack size of the secure library code
+#ifndef TZ_PROCESS_STACK_SIZE
+#define TZ_PROCESS_STACK_SIZE      256U
+#endif
+
+typedef struct {
+  uint32_t sp_top;      // stack space top
+  uint32_t sp_limit;    // stack space limit
+  uint32_t sp;          // current stack pointer
+} stack_info_t;
+
+static stack_info_t ProcessStackInfo  [TZ_PROCESS_STACK_SLOTS];
+static uint64_t     ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U];
+static uint32_t     ProcessStackFreeSlot = 0xFFFFFFFFU;
+
+
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_InitContextSystem_S (void) {
+  uint32_t n;
+
+  if (__get_IPSR() == 0U) {
+    return 0U;  // Thread Mode
+  }
+
+  for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) {
+    ProcessStackInfo[n].sp = 0U;
+    ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n];
+    ProcessStackInfo[n].sp_top   = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE;
+    *((uint32_t *)ProcessStackMemory[n]) = n + 1U;
+  }
+  *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU;
+
+  ProcessStackFreeSlot = 0U;
+
+  // Default process stack pointer and stack limit
+  __set_PSPLIM((uint32_t)ProcessStackMemory);
+  __set_PSP   ((uint32_t)ProcessStackMemory);
+
+  // Privileged Thread Mode using PSP
+  __set_CONTROL(0x02U);
+
+  return 1U;    // Success
+}
+
+
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+__attribute__((cmse_nonsecure_entry))
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) {
+  uint32_t slot;
+
+  (void)module; // Ignore (fixed Stack size)
+
+  if (__get_IPSR() == 0U) {
+    return 0U;  // Thread Mode
+  }
+
+  if (ProcessStackFreeSlot == 0xFFFFFFFFU) {
+    return 0U;  // No slot available
+  }
+
+  slot = ProcessStackFreeSlot;
+  ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]);
+
+  ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top;
+
+  return (slot + 1U);
+}
+
+
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) {
+  uint32_t slot;
+
+  if (__get_IPSR() == 0U) {
+    return 0U;  // Thread Mode
+  }
+
+  if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
+    return 0U;  // Invalid ID
+  }
+
+  slot = id - 1U;
+
+  if (ProcessStackInfo[slot].sp == 0U) {
+    return 0U;  // Inactive slot
+  }
+  ProcessStackInfo[slot].sp = 0U;
+
+  *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot;
+  ProcessStackFreeSlot = slot;
+
+  return 1U;    // Success
+}
+
+
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) {
+  uint32_t slot;
+
+  if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
+    return 0U;  // Thread Mode or using Main Stack for threads
+  }
+
+  if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
+    return 0U;  // Invalid ID
+  }
+
+  slot = id - 1U;
+
+  if (ProcessStackInfo[slot].sp == 0U) {
+    return 0U;  // Inactive slot
+  }
+
+  // Setup process stack pointer and stack limit
+  __set_PSPLIM(ProcessStackInfo[slot].sp_limit);
+  __set_PSP   (ProcessStackInfo[slot].sp);
+
+  return 1U;    // Success
+}
+
+
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) {
+  uint32_t slot;
+  uint32_t sp;
+
+  if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
+    return 0U;  // Thread Mode or using Main Stack for threads
+  }
+
+  if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
+    return 0U;  // Invalid ID
+  }
+
+  slot = id - 1U;
+
+  if (ProcessStackInfo[slot].sp == 0U) {
+    return 0U;  // Inactive slot
+  }
+
+  sp = __get_PSP();
+  if ((sp < ProcessStackInfo[slot].sp_limit) ||
+      (sp > ProcessStackInfo[slot].sp_top)) {
+    return 0U;  // SP out of range
+  }
+  ProcessStackInfo[slot].sp = sp;
+
+  // Default process stack pointer and stack limit
+  __set_PSPLIM((uint32_t)ProcessStackMemory);
+  __set_PSP   ((uint32_t)ProcessStackMemory);
+
+  return 1U;    // Success
+}

resources/Camera_driver/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/CMakeLists.txt

@@ -0,0 +1,136 @@
+cmake_minimum_required (VERSION 3.6)
+cmake_policy(SET CMP0077 NEW)
+# The tests are assuming that MATRIX_CHECK is enabled when building
+# CMSIS-DSP.
+set(MATRIXCHECK ON)
+set(FASTMATHCOMPUTATIONS OFF)
+option(DUMPPATTERN "Dump test patterns when test is failing" ON)
+
+option(CUSTOMIZE_TESTS "Enable customizations of tests" ON)
+option(BASICMATH_TESTS "Enable Basic Math testing" ON)
+option(COMPLEXMATH_TESTS "Enable Complex Math testing" ON)
+option(CONTROLLER_TESTS "Enable Controller testing" ON)
+option(FASTMATH_TESTS "Enable Fast Math testing" ON)
+option(INTRINSICS_TESTS "Enable Intrinsics testing" ON)
+option(FILTERING_TESTS "Enable Filtering testing" ON)
+option(MATRIX_TESTS "Enable Matrix testing" ON)
+option(STATISTICS_TESTS "Enable Statistics testing" ON)
+option(SUPPORT_TESTS "Enable Support testing" ON)
+option(TRANSFORM_TESTS "Enable Transform testing" ON)
+
+
+project(DSP_Lib_TestSuite)
+
+# Needed to find the config modules
+list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/..)
+
+
+set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../..)
+
+
+file(GLOB MAIN "Common/src/*.c")
+file(GLOB BASICMATH_TESTS_SRC "Common/src/basic_math_tests/*.c")
+file(GLOB COMPLEXMATH_TESTS_SRC "Common/src/complex_math_tests/*.c")
+file(GLOB CONTROLLER_TESTS_SRC "Common/src/controller_tests/*.c")
+file(GLOB FASTMATH_TESTS_SRC "Common/src/fast_math_tests/*.c")
+file(GLOB FILTERING_TESTS_SRC "Common/src/filtering_tests/*.c")
+file(GLOB INTRINSINCS_TESTS_SRC "Common/src/intrinsics_tests/*.c")
+file(GLOB MATRIX_TESTS_SRC "Common/src/matrix_tests/*.c")
+file(GLOB STATISTICS_TESTS_SRC "Common/src/statistics_tests/*.c")
+file(GLOB SUPPORT_TESTS_SRC "Common/src/support_tests/*.c")
+file(GLOB TRANSFORM_TESTS_SRC "Common/src/transform_tests/*.c")
+file(GLOB JTEST_MAIN "Common/JTest/src/*.c")
+
+set(TESTSRC ${MAIN}
+  ${BASICMATH_TESTS_SRC}
+  ${COMPLEXMATH_TESTS_SRC}
+  ${CONTROLLER_TESTS_SRC}
+  ${FASTMATH_TESTS_SRC}
+  ${FILTERING_TESTS_SRC}
+  ${INTRINSINCS_TESTS_SRC}
+  ${MATRIX_TESTS_SRC}
+  ${STATISTICS_TESTS_SRC}
+  ${SUPPORT_TESTS_SRC}
+  ${TRANSFORM_TESTS_SRC}
+  ${JTEST_MAIN}
+  )
+
+set(JINCS 
+  Common/JTest/inc
+  Common/JTest/inc/arr_desc
+  Common/inc/basic_math_tests
+  Common/inc/complex_math_tests
+  Common/inc/controller_tests
+  Common/inc/fast_math_tests
+  Common/inc/filtering_tests
+  Common/inc/intrinsics_tests
+  Common/inc/matrix_tests
+  Common/inc/statistics_tests 
+  Common/inc/support_tests 
+  Common/inc/transform_tests
+  )
+
+add_subdirectory(../Source bin_dsp)
+add_subdirectory(RefLibs bin_ref)
+
+
+add_executable(DSP_Lib_TestSuite)
+
+if (CUSTOMIZE_TESTS)
+      target_compile_definitions(DSP_Lib_TestSuite PRIVATE CUSTOMIZE_TESTS)
+endif()
+
+if (BASICMATH_TESTS)
+      target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_BASICMATH_TESTS)
+endif()
+if (COMPLEXMATH_TESTS)
+      target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_COMPLEXMATH_TESTS)
+endif()
+if (CONTROLLER_TESTS)
+      target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_CONTROLLER_TESTS)
+endif()
+if (FASTMATH_TESTS)
+      target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_FASTMATH_TESTS)
+endif()
+if (FILTERING_TESTS)
+      target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_FILTERING_TESTS)
+endif()
+if (INTRINSICS_TESTS)
+      target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_INTRINSICS_TESTS)
+endif()
+if (MATRIX_TESTS)
+      target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_MATRIX_TESTS)
+endif()
+if (STATISTICS_TESTS)
+      target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_STATISTICS_TESTS)
+endif()
+if (SUPPORT_TESTS)
+      target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_SUPPORT_TESTS)
+endif()
+if (TRANSFORM_TESTS)
+      target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_TRANSFORM_TESTS)
+endif()
+
+
+if (DUMPPATTERN)
+      target_compile_definitions(DSP_Lib_TestSuite PRIVATE DUMPPATTERN)
+endif()
+
+# Change behavior of configBoot for scatter file
+set(TESTFRAMEWORK ON)
+
+include(configBoot)
+
+file(COPY ${ROOT}/CMSIS/DSP/Examples/ARM/boot/RTE_Components.h DESTINATION tempLink)
+
+target_link_libraries(DSP_Lib_TestSuite PRIVATE CMSISDSP)
+target_link_libraries(DSP_Lib_TestSuite PRIVATE DspRefLibs)
+
+target_sources(DSP_Lib_TestSuite PRIVATE ${TESTSRC})
+
+### Includes
+target_include_directories(DSP_Lib_TestSuite PRIVATE "Common/inc")
+target_include_directories(DSP_Lib_TestSuite PRIVATE "Common/inc/templates")
+target_include_directories(DSP_Lib_TestSuite PRIVATE ${JINCS})
+
+

resources/Camera_driver/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/arr_desc/arr_desc.h

@@ -0,0 +1,220 @@
+#ifndef _ARR_DESC_H_
+#define _ARR_DESC_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+#include <stdint.h>
+#include <string.h>             /* memset() */
+#include "../util/util.h"       /* CONCAT() */
+
+/*--------------------------------------------------------------------------------*/
+/* Type Definitions */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Array-descriptor struct.
+ */
+typedef struct ARR_DESC_struct
+{
+    void *  data_ptr;                /* Pointer to the array contents. */
+    int32_t element_count;           /* Number of current elements. */
+    int32_t element_size;            /* Size of current elements in bytes. */
+    int32_t underlying_size;         /* Size of underlying array in bytes. */
+} ARR_DESC_t;
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Prefix of the array variable's name when creating an array and an array
+ *  descriptor at the same time.
+ */
+#define ARR_DESC_ARR_PREFIX ARR_DESC_ARR_
+
+/**
+ *  Evaluate to the array variable's name when creating an array and an array
+ *  descriptor at the same time.
+ */
+#define ARR_DESC_ARR_NAME(name)                 \
+    CONCAT(ARR_DESC_ARR_PREFIX, name)
+
+/**
+ *  Define an #ARR_DESC_t by itself.
+ *
+ *  @note The user must supply an array to store the data used by the
+ *  #ARR_DESC_t.
+ */
+#define ARR_DESC_INTERNAL_DEFINE(name, data_ptr,                \
+                                 element_count, element_size)   \
+    ARR_DESC_t name = {                                         \
+        data_ptr,                                               \
+        element_count,                                          \
+        element_size,                                           \
+        element_count * element_size                            \
+    }                                                           \
+
+/**
+ *  Define both an array and an #ARR_DESC_t that describes it.
+ *
+ *  @note Use the #CURLY() macro for the content field; it provides the curly
+ *  braces necessary for an array initialization.
+ */
+#define ARR_DESC_DEFINE(type, name, element_count, content)             \
+    type ARR_DESC_ARR_NAME(name)[element_count] = content;              \
+    ARR_DESC_INTERNAL_DEFINE(name,                                      \
+                             &ARR_DESC_ARR_NAME(name),                  \
+                             element_count,                             \
+                             sizeof(type)) /* Note the lacking semicolon */
+
+/**
+ *  Create a #ARR_DESC_t which refers to a subset of the data in another.
+ *
+ *  The new #ARR_DESC_t shares the same underlying array as the aliased
+ *  #ARR_DESC_t, but only describes a subset of the originals values.
+ */
+#define ARR_DESC_DEFINE_SUBSET(name, original, element_cnt)         \
+    ARR_DESC_INTERNAL_DEFINE(name,                                  \
+                             &ARR_DESC_ARR_NAME(original),          \
+                             element_cnt,                           \
+                             sizeof(ARR_DESC_ARR_NAME(original)[0]) \
+        ) /* Note the lacking semicolon */
+
+/**
+ *  Creat an #ARR_DESC_t which points to the data in an existing array.
+ *
+ *  @param start_idx Offset in array_ptr of first element.
+ *  @param element_cnt Number of elements to include in the #ARR_DESC_t.
+ *
+ *  @example
+ *
+ *  float my_floats[4] = {0.0f, 1.0f, 2.0f, 3.0f};
+ *
+ *  ARR_DESC_DEFINE_USING_ARR(my_arr_desc, my_floats, 1, 3);
+ *
+ *  printf("Element 0: %f\n", ARR_DESC_ELT(float, 0, &my_arr_desc));
+ *  printf("Element 1: %f\n", ARR_DESC_ELT(float, 1, &my_arr_desc));
+ *
+ *  Outputs:
+ *
+ *  Element 0: 1.000000
+ *  Element 1: 2.000000
+ *
+ *  @warning There are no checks in place to catch invalid start indices; This
+ *  is left to the user.
+ */
+#define ARR_DESC_DEFINE_USING_ARR(type, name, array_ptr, start_idx, element_cnt) \
+    ARR_DESC_INTERNAL_DEFINE(                                           \
+        name,                                                           \
+        (type *) (array_ptr + start_idx),                               \
+        element_cnt,                                                    \
+        sizeof(type)                                                    \
+        ) /* Note the lacking semicolon*/
+
+/**
+ *  Declare an #ARR_DESC_t object.
+ */
+#define ARR_DESC_DECLARE(name)                              \
+    extern ARR_DESC_t name /* Note the lacking semicolon */
+
+/**
+ *  Evaluate to the number of bytes stored in the #ARR_DESC_t.
+ */
+#define ARR_DESC_BYTES(arr_desc_ptr)                                \
+    ((arr_desc_ptr)->element_count * (arr_desc_ptr)->element_size)
+
+/**
+ *  Set the contents of #ARR_DESC_t to value.
+ */
+#define ARR_DESC_MEMSET(arr_desc_ptr, value, bytes)     \
+    do                                                  \
+    {                                                   \
+        memset((arr_desc_ptr)->data_ptr,                \
+               value,                                   \
+               BOUND(0,                                 \
+                     (arr_desc_ptr)->underlying_size,   \
+                     bytes)                             \
+            );                                          \
+    } while (0)
+
+/**
+ *  Perform a memcpy of 'bytes' bytes from the source #ARR_DESC_t to the
+ *  destination #ARR_DESC_t.
+ */
+#define ARR_DESC_MEMCPY(arr_desc_dest_ptr, arr_desc_src_ptr, bytes) \
+    do                                                              \
+    {                                                               \
+        memcpy((arr_desc_dest_ptr)->data_ptr,                       \
+               (arr_desc_src_ptr)->data_ptr,                        \
+               BOUND(0,                                             \
+                     (arr_desc_dest_ptr)->underlying_size,          \
+                     bytes));                                       \
+    } while (0)
+
+/**
+ *  Evaluate to true if the source #ARR_DESC_t contents will fit into the
+ *  destination #ARR_DESC_t and false otherwise.
+ */
+#define ARR_DESC_COPYABLE(arr_desc_dest_ptr, arr_desc_src_ptr)  \
+      (ARR_DESC_BYTES(arr_desc_src_ptr) <=                      \
+       (arr_desc_dest_ptr)->underlying_size)
+
+/**
+ *  Copy all the data from the source #ARR_DESC_t to the destination
+ *  #ARR_DESC_t.
+ *
+ *  @note If the destination #ARR_DESC_t is too small to fit the source data the
+ *  copy is aborted and nothing happens.
+ */
+#define ARR_DESC_COPY(arr_desc_dest_ptr, arr_desc_src_ptr)      \
+    do                                                          \
+    {                                                           \
+        if (ARR_DESC_COPYABLE(arr_desc_dest_ptr,                 \
+                             arr_desc_src_ptr))                 \
+        {                                                       \
+            ARR_DESC_MEMCPY(arr_desc_dest_ptr,                  \
+                            arr_desc_src_ptr,                   \
+                            ARR_DESC_BYTES(arr_desc_src_ptr));  \
+            /* Update the properties*/                          \
+            (arr_desc_dest_ptr)->element_count =                \
+                (arr_desc_src_ptr)->element_count;              \
+            (arr_desc_dest_ptr)->element_size =                 \
+                (arr_desc_src_ptr)->element_size;               \
+        }                                                       \
+    } while (0)
+
+/**
+ *  Compare the data in two #ARR_DESC_t structs for the specified number of
+ *  bytes.
+ */
+#define ARR_DESC_MEMCMP(arr_desc_ptr_a, arr_desc_ptr_b, bytes)  \
+        memcmp((arr_desc_ptr_a)->data_ptr,                      \
+            (arr_desc_ptr_b)->data_ptr,                         \
+               bytes) /* Note the lacking semicolon */          \
+
+/**
+ *  Zero out the contents of the #ARR_DESC_t.
+ */
+#define ARR_DESC_ZERO(arr_desc_ptr)             \
+        ARR_DESC_MEMSET(arr_desc_ptr,           \
+                        0,                      \
+                        (arr_desc_ptr)->underlying_size)
+
+/**
+ *  Evaluate to the data address in #ARR_DESC_t at offset.
+ */
+#define ARR_DESC_DATA_ADDR(type, arr_desc_ptr, offset)  \
+        ((void*)(((type *)                              \
+                  ((arr_desc_ptr)->data_ptr))           \
+                 + offset))
+
+/**
+ *  Evaluate to the element in #ARR_DESC_t with type at idx.
+ */
+#define ARR_DESC_ELT(type, idx, arr_desc_ptr)           \
+        (*((type *) ARR_DESC_DATA_ADDR(type,            \
+                                       arr_desc_ptr,    \
+                                       idx)))
+
+#endif /* _ARR_DESC_H_ */

resources/Camera_driver/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest.h

@@ -0,0 +1,17 @@
+#ifndef _JTEST_H_
+#define _JTEST_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "jtest_fw.h"
+#include "jtest_test.h"
+#include "jtest_test_define.h"
+#include "jtest_test_call.h"
+#include "jtest_group.h"
+#include "jtest_group_define.h"
+#include "jtest_group_call.h"
+#include "jtest_cycle.h"
+
+#endif /* _JTEST_H_ */

resources/Camera_driver/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_cycle.h

@@ -0,0 +1,79 @@
+#ifndef _JTEST_CYCLE_H_
+#define _JTEST_CYCLE_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "jtest_fw.h"           /* JTEST_DUMP_STRF() */
+#include "jtest_systick.h"
+#include "jtest_util.h"         /* STR() */
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Module Variables */
+/*--------------------------------------------------------------------------------*/
+extern const char * JTEST_CYCLE_STRF;
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Wrap the function call, fn_call, to count execution cycles and display the
+ *  results.
+ */
+/* skipp function name + param
+#define JTEST_COUNT_CYCLES(fn_call)                     \
+    do                                                  \
+    {                                                   \
+        uint32_t __jtest_cycle_end_count;               \
+                                                        \
+        JTEST_SYSTICK_RESET(SysTick);                   \
+        JTEST_SYSTICK_START(SysTick);                   \
+                                                        \
+        fn_call;                                        \
+                                                        \
+        __jtest_cycle_end_count =                       \
+            JTEST_SYSTICK_VALUE(SysTick);               \
+                                                        \
+		JTEST_SYSTICK_RESET(SysTick);                   \
+        JTEST_DUMP_STRF(JTEST_CYCLE_STRF,               \
+                        STR(fn_call),                   \
+                        (JTEST_SYSTICK_INITIAL_VALUE -  \
+                         __jtest_cycle_end_count));     \
+    } while (0)
+*/
+#ifndef ARMv7A
+
+#define JTEST_COUNT_CYCLES(fn_call)                     \
+    do                                                  \
+    {                                                   \
+        uint32_t __jtest_cycle_end_count;               \
+                                                        \
+        JTEST_SYSTICK_RESET(SysTick);                   \
+        JTEST_SYSTICK_START(SysTick);                   \
+                                                        \
+        fn_call;                                        \
+                                                        \
+        __jtest_cycle_end_count =                       \
+            JTEST_SYSTICK_VALUE(SysTick);               \
+                                                        \
+		JTEST_SYSTICK_RESET(SysTick);           \
+        JTEST_DUMP_STRF(JTEST_CYCLE_STRF,               \
+                        (JTEST_SYSTICK_INITIAL_VALUE -  \
+                         __jtest_cycle_end_count));     \
+    } while (0)
+
+#else
+/* TODO */
+#define JTEST_COUNT_CYCLES(fn_call)                     \
+    do                                                  \
+    {                                                   \
+		fn_call;   										\
+    } while (0)
+
+#endif
+
+#endif /* _JTEST_CYCLE_H_ */
+
+

resources/Camera_driver/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_define.h

@@ -0,0 +1,37 @@
+#ifndef _JTEST_DEFINE_H_
+#define _JTEST_DEFINE_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Makes a symbol for use as a struct name. Names made this way have two parts;
+ *  the first parts is a prefix common to all structs of that class. The second
+ *  is a specifier which differs for each instance of that struct type.
+ */
+#define JTEST_STRUCT_NAME(prefix, specifier)    \
+    CONCAT(prefix, specifier)
+
+/**
+ *  Define a struct with type with a name generated by #JTEST_STRUCT_NAME().
+ */
+#define JTEST_DEFINE_STRUCT(type, struct_name)    \
+    type struct_name
+
+/**
+ *  Declare a struct with type with a name generated by #JTEST_STRUCT_NAME().
+ */
+#define JTEST_DECLARE_STRUCT(struct_definition) \
+    extern struct_definition
+
+/**
+ *  Define and initialize a struct (created with JTEST_DEFINE_STRUCT()) and
+ *  initialize it with init_values.
+ */
+#define JTEST_INIT_STRUCT(struct_definition, init_values)       \
+    struct_definition = {                                       \
+        init_values                                             \
+    }
+
+#endif /* _JTEST_DEFINE_H_ */

resources/Camera_driver/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_fw.h

@@ -0,0 +1,282 @@
+#ifndef _JTEST_FW_H_
+#define _JTEST_FW_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include <stdint.h>             /* int32_t */
+#include <string.h>             /* strcpy() */
+#include <stdio.h>              /* sprintf() */
+#include "jtest_pf.h"           /* Extend JTEST_FW_t with Pass/Fail data */
+#include "jtest_group.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Type Definitions */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  A struct used to interface with the Keil Debugger.
+ */
+typedef struct JTEST_FW_struct
+{
+    /* Action Triggers: The Keil debugger monitors these values for changes.  In
+     * response to a change, the debugger executes code on the host. */
+    volatile int32_t test_start;
+    volatile int32_t test_end;
+    volatile int32_t group_start;
+    volatile int32_t group_end;
+    volatile int32_t dump_str;
+    volatile int32_t dump_data;
+    volatile int32_t exit_fw;
+
+    JTEST_GROUP_t * current_group_ptr;
+
+    /* Buffers: The C-code cannot send strings and data directly to the
+     * debugging framework. Instead, the debugger can be told to read 128 byte
+     * (by default) chunks of memory.  Data received in this manner requires
+     * post-processing to be legible.*/
+    char * str_buffer;
+    char * data_buffer;
+
+    /* Pass/Fail Data */
+    JTEST_PF_MEMBERS;
+
+} JTEST_FW_t;
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Default name for the JTEST_FW struct.
+ *
+ *  Define your own if you want the variable containing the #JTEST_FW_t to have
+ *  a different name.
+ */
+#ifndef JTEST_FW
+#define JTEST_FW JTEST_FW
+#endif
+
+/**
+ *  Default name for the JTEST_FW_STR_BUFFER.
+ *
+ *  Define your own if you want the variable containing the char buffer to have
+ *  a different name.
+ */
+#ifndef JTEST_FW_STR_BUFFER
+#define JTEST_FW_STR_BUFFER JTEST_FW_STR_BUFFER
+#endif
+
+/**
+ *  Size of the #JTEST_FW_t, output string-buffer.
+ *
+ *  If you change this value, make sure the "dump_str_fn" and "dump_data_fn"
+ *  functions in jtest_fns.ini uses the same size. If you aren't sure, read the
+ *  documentation Keil Debugger Command 'DISPLAY'.
+ */
+#define JTEST_BUF_SIZE 256
+
+
+/**
+ *  The maximum number of bytes output at once using #JTEST_DUMP_STRF().
+ */
+#define JTEST_STR_MAX_OUTPUT_SIZE 128
+
+/**
+ *  The maximum number of block transimissions needed to send a string from a
+ *  buffer with JTEST_BUF_SIZE.
+ */
+#define JTEST_STR_MAX_OUTPUT_SEGMENTS           \
+    (JTEST_BUF_SIZE / JTEST_STR_MAX_OUTPUT_SIZE)
+
+/**
+ *  Initialize the JTEST framework.
+ */
+#define JTEST_INIT()                                                    \
+    do                                                                  \
+    {                                                                   \
+        JTEST_FW.str_buffer = JTEST_FW_STR_BUFFER;                      \
+    } while (0)
+
+/* Debugger Action-triggering Macros */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Dispatch macro to trigger various actions in the Keil Debugger.
+ */
+#define JTEST_TRIGGER_ACTION(action_name)       \
+    do                                          \
+    {                                           \
+        action_name();                          \
+    } while (0)
+
+/**
+ *  Trigger the "Test Start" action in the Keil Debugger.
+ */
+#define JTEST_ACT_TEST_START()                  \
+    JTEST_TRIGGER_ACTION(test_start)
+
+/**
+ *  Trigger the "Test End" action in the Keil Debugger.
+ */
+#define JTEST_ACT_TEST_END()                    \
+    JTEST_TRIGGER_ACTION(test_end)
+
+
+/**
+ *  Trigger the "Group Start" action in the Keil Debugger.
+ */
+#define JTEST_ACT_GROUP_START()                 \
+    JTEST_TRIGGER_ACTION(group_start)
+
+/**
+ *  Trigger the "Group End" action in the Keil Debugger.
+ */
+#define JTEST_ACT_GROUP_END()                   \
+    JTEST_TRIGGER_ACTION(group_end)
+
+
+/**
+ *  Fill the buffer named buf_name with value and dump it to the Keil debugger
+ *  using action.
+ */
+#if defined(ARMv7A) || defined(FILEIO)
+
+#define JTEST_ACT_DUMP(action, buf_name, value) \
+    do                                          \
+    {                                           \
+        JTEST_CLEAR_BUFFER(buf_name);           \
+	    printf("%s",value);                     \
+        strcpy(JTEST_FW.buf_name, (value));     \
+        JTEST_TRIGGER_ACTION(action);           \
+    } while (0)
+
+#else
+
+#define JTEST_ACT_DUMP(action, buf_name, value) \
+    do                                          \
+    {                                           \
+        JTEST_CLEAR_BUFFER(buf_name);           \
+        strcpy(JTEST_FW.buf_name, (value));     \
+        JTEST_TRIGGER_ACTION(action);           \
+    } while (0)
+
+#endif
+/**
+ *  Trigger the "Exit Framework" action in the Keil Debugger.
+ */
+#define JTEST_ACT_EXIT_FW()                     \
+    do                                          \
+    {                                           \
+        JTEST_TRIGGER_ACTION(exit_fw);          \
+    } while (0)
+
+
+/* Buffer Manipulation Macros */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Clear the JTEST_FW buffer with name buf_name.
+ */
+#define JTEST_CLEAR_BUFFER(buf_name)                    \
+    do                                                  \
+    {                                                   \
+        memset(JTEST_FW.buf_name, 0, JTEST_BUF_SIZE);   \
+    } while (0)
+
+/**
+ *  Clear the memory needed for the JTEST_FW's string buffer.
+ */
+#define JTEST_CLEAR_STR_BUFFER()                \
+        JTEST_CLEAR_BUFFER(str_buffer)
+
+/**
+ *  Clear the memory needed for the JTEST_FW's data buffer.
+ */
+#define JTEST_CLEAR_DATA_BUFFER()               \
+        JTEST_CLEAR_BUFFER(data_buffer)
+
+/**
+ *  Dump the given string to the Keil Debugger.
+ */
+#define JTEST_DUMP_STR(string)                          \
+        JTEST_ACT_DUMP(dump_str, str_buffer, string)
+
+/**
+ *  Dump a formatted string to the Keil Debugger.
+ */
+#if defined(ARMv7A) || defined(FILEIO)
+
+#define JTEST_DUMP_STRF(format_str, ... )                               \
+    do                                                                  \
+    {                                                                   \
+        JTEST_CLEAR_STR_BUFFER();                                       \
+        sprintf(JTEST_FW.str_buffer,format_str, __VA_ARGS__);           \
+        printf("%s",JTEST_FW.str_buffer);                               \
+        jtest_dump_str_segments();                                      \
+    } while (0)
+
+#else
+
+#define JTEST_DUMP_STRF(format_str, ... )                               \
+    do                                                                  \
+    {                                                                   \
+        JTEST_CLEAR_STR_BUFFER();                                       \
+        sprintf(JTEST_FW.str_buffer,format_str, __VA_ARGS__);           \
+        jtest_dump_str_segments();                                      \
+    } while (0)
+
+#endif
+
+/* Pass/Fail Macros */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Increment the number of passed tests in #JTEST_FW.
+ */
+#define JTEST_FW_INC_PASSED(amount)             \
+        JTEST_PF_INC_PASSED(&JTEST_FW, amount)
+
+/**
+ *  Increment the number of passed tests in #JTEST_FW.
+ */
+#define JTEST_FW_INC_FAILED(amount)             \
+        JTEST_PF_INC_FAILED(&JTEST_FW, amount)
+
+/* Manipulating the Current Group */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Evaluate to the current_group_ptr in #JTEST_FW.
+ */
+#define JTEST_CURRENT_GROUP_PTR()               \
+    (JTEST_FW.current_group_ptr)
+
+#define JTEST_SET_CURRENT_GROUP(group_ptr)      \
+    do                                          \
+    {                                           \
+        JTEST_CURRENT_GROUP_PTR() = group_ptr;  \
+    } while (0)
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Global Variables */
+/*--------------------------------------------------------------------------------*/
+extern char JTEST_FW_STR_BUFFER[JTEST_BUF_SIZE];
+extern volatile JTEST_FW_t JTEST_FW;
+
+/*--------------------------------------------------------------------------------*/
+/* Function Prototypes */
+/*--------------------------------------------------------------------------------*/
+void jtest_dump_str_segments(void);
+
+void test_start  (void);
+void test_end    (void);
+void group_start (void);
+void group_end   (void);
+void dump_str    (void);
+void dump_data   (void);
+void exit_fw     (void);
+
+
+#endif /* _JTEST_FW_H_ */

resources/Camera_driver/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group.h

@@ -0,0 +1,66 @@
+#ifndef _JTEST_GROUP_H_
+#define _JTEST_GROUP_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "jtest_pf.h"
+#include "jtest_util.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Type Definitions */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  A struct which represents a group of #JTEST_TEST_t structs. This struct is
+ *  used to run the group of tests, and report on their outcomes.
+ */
+typedef struct JTEST_GROUP_struct
+{
+    void (* group_fn_ptr) (void); /**< Pointer to the test group */
+    char * name_str;              /**< Name of the group */
+    
+    /* Extend the #JTEST_GROUP_t with Pass/Fail information.*/
+    JTEST_PF_MEMBERS;
+} JTEST_GROUP_t;
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Set the name of JTEST_GROUP_t.
+ */
+#define JTEST_GROUP_SET_NAME(group_ptr, name)     \
+    JTEST_SET_STRUCT_ATTRIBUTE(group_ptr, name_str, name)
+
+#define JTEST_GROUP_SET_FN(group_ptr, fn_ptr)     \
+    JTEST_SET_STRUCT_ATTRIBUTE(group_ptr, group_fn_ptr, fn_ptr)
+
+/**
+ *  Increment the number of tests passed in the JTEST_GROUP_t pointed to by
+ *  group_ptr.
+ */
+#define JTEST_GROUP_INC_PASSED(group_ptr, amount) \
+    JTEST_PF_INC_PASSED(group_ptr, amount)
+
+/**
+ *  Increment the number of tests failed in the JTEST_GROUP_t pointed to by
+ *  group_ptr.
+ */
+#define JTEST_GROUP_INC_FAILED(group_ptr, amount) \
+    JTEST_PF_INC_FAILED(group_ptr, amount)
+
+/**
+ *  Reset the pass/fail information of the #JTEST_GROUP_t pointed to by
+ *  group_ptr.
+ */
+#define JTEST_GROUP_RESET_PF(group_ptr)         \
+    do                                          \
+    {                                           \
+        JTEST_PF_RESET_PASSED(group_ptr);       \
+        JTEST_PF_RESET_FAILED(group_ptr);       \
+    } while (0)
+
+#endif /* _JTEST_GROUP_H_ */

resources/Camera_driver/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group_call.h

@@ -0,0 +1,126 @@
+#ifndef _JTEST_GROUP_CALL_H_
+#define _JTEST_GROUP_CALL_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "jtest_fw.h"
+#include <inttypes.h>
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Execute the test in the #JTEST_GROUP_t struct associated witht he identifier
+ *  group_fn.
+ */
+#define JTEST_GROUP_RUN(group_fn)                                   \
+    do                                                              \
+    {                                                               \
+        JTEST_DUMP_STR("Group Name:\n");                            \
+        JTEST_DUMP_STR(JTEST_GROUP_STRUCT_NAME(group_fn).name_str); \
+        JTEST_GROUP_STRUCT_NAME(group_fn).group_fn_ptr();           \
+    } while (0)
+
+
+/**
+ *  Update the enclosing #JTEST_GROUP_t's pass/fail information using the
+ *  current #JTEST_GROUP_t's.
+ *
+ *  @param group_ptr Pointer to the current #JTEST_GROUP_t.
+ *  @param parent_ptr Pointer to the enclosing #JTEST_GROUP_t.
+ *
+ *  @warning Only run this if the current #JTEST_GROUP_t is being called within
+ *  the context of another #JTEST_GROUP_t.
+ */
+#define JTEST_GROUP_UPDATE_PARENT_GROUP_PF(group_ptr, parent_group_ptr) \
+    do                                                                  \
+    {                                                                   \
+        JTEST_GROUP_INC_PASSED(parent_group_ptr,                        \
+                               (group_ptr)->passed);                    \
+        JTEST_GROUP_INC_FAILED(parent_group_ptr,                        \
+                               (group_ptr)->failed);                    \
+    } while (0)
+
+/**
+ *  Update the #JTEST_FW's pass/fail information using the current
+ *  #JTEST_GROUP_t's.
+ */
+#define JTEST_GROUP_UPDATE_FW_PF(group_ptr)                     \
+    do                                                          \
+    {                                                           \
+        JTEST_FW_INC_PASSED((group_ptr)->passed);               \
+        JTEST_FW_INC_FAILED((group_ptr)->failed);               \
+    } while (0)
+
+/**
+ *  Update the enclosing context with the current #JTEST_GROUP_t's pass/fail
+ *  information. If this group isn't in an enclosing group, it updates the
+ *  #JTEST_FW's pass/fail info by default.
+ */
+#define JTEST_GROUP_UPDATE_PARENT_GROUP_OR_FW_PF(group_ptr,         \
+                                                 parent_group_ptr)  \
+    do                                                              \
+    {                                                               \
+        /* Update the pass fail counts in the parent group */       \
+        if (parent_group_ptr /* Null implies Top*/)                 \
+        {                                                           \
+            JTEST_GROUP_UPDATE_PARENT_GROUP_PF(                     \
+                group_ptr,                                          \
+                parent_group_ptr);                                  \
+        } else {                                                    \
+            JTEST_GROUP_UPDATE_FW_PF(                               \
+                group_ptr);                                         \
+        }                                                           \
+    } while (0)
+
+/**
+ *  Dump the results of running the #JTEST_GROUP_t to the Keil Debugger.
+ */
+#define JTEST_GROUP_DUMP_RESULTS(group_ptr)                             \
+        do                                                              \
+        {                                                               \
+            JTEST_DUMP_STRF(                                            \
+                "Tests Run: %" PRIu32 "\n"                              \
+                "----------\n"                                          \
+                "   Passed: %" PRIu32 "\n"                              \
+                "   Failed: %" PRIu32 "\n",                             \
+                (group_ptr)->passed + (group_ptr)->failed,              \
+                (group_ptr)->passed,                                    \
+                (group_ptr)->failed);                                   \
+        } while (0)
+
+/**
+ *  Call the #JTEST_GROUP_t associated with the identifier group_fn.
+ */
+#define JTEST_GROUP_CALL(group_fn)                                      \
+        do                                                              \
+        {   /* Save the current group from JTEST_FW_t before swapping */ \
+            /* it to this group (in order to restore it later )*/       \
+            JTEST_GROUP_t * __jtest_temp_group_ptr =                    \
+                JTEST_CURRENT_GROUP_PTR();                              \
+            JTEST_SET_CURRENT_GROUP(&JTEST_GROUP_STRUCT_NAME(group_fn)); \
+                                                                        \
+            /* Reset this group's pass/fail count. Each group */        \
+            /* should only remember counts for its last execution. */   \
+            JTEST_GROUP_RESET_PF(JTEST_CURRENT_GROUP_PTR());            \
+                                                                        \
+            /* Run the current group */                                 \
+            JTEST_ACT_GROUP_START();                                    \
+            JTEST_GROUP_RUN(group_fn);                                  \
+            JTEST_ACT_GROUP_END();                                      \
+                                                                        \
+            /* Update the pass fail counts in the parent group (or FW) */ \
+            JTEST_GROUP_UPDATE_PARENT_GROUP_OR_FW_PF(                   \
+                JTEST_CURRENT_GROUP_PTR(),                              \
+                __jtest_temp_group_ptr);                                \
+                                                                        \
+            JTEST_GROUP_DUMP_RESULTS(JTEST_CURRENT_GROUP_PTR());        \
+                                                                        \
+            /* Restore the previously current group */                  \
+            JTEST_SET_CURRENT_GROUP(__jtest_temp_group_ptr);            \
+        } while (0)
+
+#endif /* _JTEST_GROUP_CALL_H_ */

resources/Camera_driver/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group_define.h

@@ -0,0 +1,87 @@
+#ifndef _JTEST_GROUP_DEFINE_H_
+#define _JTEST_GROUP_DEFINE_H_
+
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "jtest_util.h"
+#include "jtest_define.h"
+#include "jtest_group.h"
+
+/* For defining macros with optional arguments */
+#include "opt_arg/opt_arg.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Prefix for all #JTEST_GROUP_t structs.
+ */
+#define JTEST_GROUP_STRUCT_NAME_PREFIX G_JTEST_GROUP_STRUCT_
+
+/**
+ *  Define test template used by #JTEST_GROUP_t tests.
+ */
+#define JTEST_GROUP_FN_TEMPLATE(group_fn)    \
+    void group_fn(void)
+
+#define JTEST_GROUP_FN_PROTOTYPE JTEST_GROUP_FN_TEMPLATE /**< Alias for
+                                                            #JTEST_GROUP_FN_TEMPLATE. */
+
+/**
+ *  Evaluate to the name of the #JTEST_GROUP_t struct associated with group_fn.
+ */
+#define JTEST_GROUP_STRUCT_NAME(group_fn)    \
+    JTEST_STRUCT_NAME(JTEST_GROUP_STRUCT_NAME_PREFIX, group_fn)
+
+/**
+ *  Define a #JTEST_GROUP_t struct based on the given group_fn.
+ */
+#define JTEST_GROUP_DEFINE_STRUCT(group_fn)  \
+    JTEST_DEFINE_STRUCT(JTEST_GROUP_t,       \
+                        JTEST_GROUP_STRUCT_NAME(group_fn))
+
+/**
+ *  Declare a #JTEST_GROUP_t struct based on the given group_fn.
+ */
+#define JTEST_GROUP_DECLARE_STRUCT(group_fn) \
+    JTEST_DECLARE_STRUCT(JTEST_GROUP_DEFINE_STRUCT(group_fn))
+
+/**
+ *  Contents needed to initialize a JTEST_GROUP_t struct.
+ */
+#define JTEST_GROUP_STRUCT_INIT(group_fn)    \
+    group_fn,                                \
+        STR_NL(group_fn),                       \
+        JTEST_PF_MEMBER_INIT
+
+/**
+ *  Initialize the contents of a #JTEST_GROUP_t struct.
+ */
+#define JTEST_GROUP_INIT(group_fn)           \
+    JTEST_GROUP_DEFINE_STRUCT(group_fn) = {  \
+        JTEST_GROUP_STRUCT_INIT(group_fn)    \
+    }
+
+/* Test Definition Macro */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Define a #JTEST_GROUP_t object and a test function.
+ */
+#define JTEST_DEFINE_GROUP(group_fn)         \
+    JTEST_GROUP_FN_PROTOTYPE(group_fn);      \
+    JTEST_GROUP_INIT(group_fn);              \
+    JTEST_GROUP_FN_PROTOTYPE(group_fn) /* Notice the lacking semicolon */
+
+/**
+ *  Declare a #JTEST_GROUP_t object and a test function prototype.
+ */
+#define JTEST_DECLARE_GROUP(group_fn)        \
+    JTEST_GROUP_FN_PROTOTYPE(group_fn);      \
+    JTEST_GROUP_DECLARE_STRUCT(group_fn) /* Note the lacking semicolon */
+
+#endif /* _JTEST_GROUP_DEFINE_H_ */

resources/Camera_driver/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_pf.h

@@ -0,0 +1,85 @@
+#ifndef _JTEST_PF_H_
+#define _JTEST_PF_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Purpose */
+/*--------------------------------------------------------------------------------*/
+/* jtest_pf.h Contains macros useful for capturing pass/fail data. */
+
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Members that can be added to other structs to extend them pass/fail data and
+ * corresponding functionality.
+ */
+#define JTEST_PF_MEMBERS                            \
+    uint32_t passed;                                \
+    uint32_t failed /* Note the lacking semicolon*/ \
+
+/**
+ *  Used for initializing JTEST_PF_MEMBERS in a struct declaration.
+ */
+#define JTEST_PF_MEMBER_INIT                    \
+    0,                                          \
+    0
+
+/* Member-Incrementing Macros */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Dispatch macro for incrementing #JTEST_PF_MEMBERS.
+ *
+ *  @param xxx Values: 'passed', 'failed'
+ */
+#define JTEST_PF_INC_XXX(xxx, struct_pf_ptr, amount)    \
+    do                                                  \
+    {                                                   \
+        ((struct_pf_ptr)->xxx) += (amount);             \
+    } while (0)
+
+/**
+ *  Specialization of the #JTEST_PF_INC_XXX macro to increment the passed
+ *  member.
+ */
+#define JTEST_PF_INC_PASSED(struct_pf_ptr, amount)  \
+    JTEST_PF_INC_XXX(passed, struct_pf_ptr, amount)
+
+
+/**
+ *  Specialization of the #JTEST_PF_INC_XXX macro to increment the failed
+ *  member.
+ */
+#define JTEST_PF_INC_FAILED(struct_pf_ptr, amount)  \
+    JTEST_PF_INC_XXX(failed, struct_pf_ptr, amount)
+
+
+/* Member-Resetting Macros */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Dispatch macro for setting #JTEST_PF_MEMBERS to zero.
+ *
+ *  @param xxx Values: 'passed', 'failed'
+ */
+#define JTEST_PF_RESET_XXX(xxx, struct_pf_ptr)  \
+    do                                          \
+    {                                           \
+        ((struct_pf_ptr)->xxx) = UINT32_C(0);   \
+    } while (0)
+
+/**
+ *  Specialization of #JTEST_PF_RESET_XXX for the 'passed' member.
+ */
+#define JTEST_PF_RESET_PASSED(struct_pf_ptr)    \
+    JTEST_PF_RESET_XXX(passed, struct_pf_ptr)
+
+/**
+ *  Specialization of #JTEST_PF_RESET_XXX for the 'failed' member.
+ */
+#define JTEST_PF_RESET_FAILED(struct_pf_ptr)    \
+    JTEST_PF_RESET_XXX(failed, struct_pf_ptr)
+
+#endif /* _JTEST_PF_H_ */

resources/Camera_driver/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_systick.h

@@ -0,0 +1,94 @@
+#ifndef _JTEST_SYSTICK_H_
+#define _JTEST_SYSTICK_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes                                                                       */
+/*--------------------------------------------------------------------------------*/
+
+/* Get access to the SysTick structure. */
+#if   defined ARMCM0
+  #include "ARMCM0.h"
+#elif defined ARMCM0P
+  #include "ARMCM0plus.h"
+#elif defined ARMCM0P_MPU
+  #include "ARMCM0plus_MPU.h"
+#elif defined ARMCM3
+  #include "ARMCM3.h"
+#elif defined ARMCM4
+  #include "ARMCM4.h"
+#elif defined ARMCM4_FP
+  #include "ARMCM4_FP.h"
+#elif defined ARMCM7
+  #include "ARMCM7.h" 
+#elif defined ARMCM7_SP
+  #include "ARMCM7_SP.h"
+#elif defined ARMCM7_DP
+  #include "ARMCM7_DP.h"
+#elif defined ARMSC000
+  #include "ARMSC000.h"
+#elif defined ARMSC300
+  #include "ARMSC300.h"
+#elif defined ARMv8MBL
+  #include "ARMv8MBL.h"
+#elif defined ARMv8MML
+  #include "ARMv8MML.h"
+#elif defined ARMv8MML_DSP
+  #include "ARMv8MML_DSP.h"
+#elif defined ARMv8MML_SP
+  #include "ARMv8MML_SP.h"
+#elif defined ARMv8MML_DSP_SP
+  #include "ARMv8MML_DSP_SP.h"
+#elif defined ARMv8MML_DP
+  #include "ARMv8MML_DP.h"
+#elif defined ARMv8MML_DSP_DP
+  #include "ARMv8MML_DSP_DP.h"
+#elif defined ARMv7A
+  /* TODO */
+#else
+  #warning "no appropriate header file found!"
+#endif
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines                                                             */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Initial value for the SysTick module.
+ *
+ *  This is also the maximum value, important as SysTick is a decrementing counter.
+ */
+#define JTEST_SYSTICK_INITIAL_VALUE       0xFFFFFF
+
+/**
+ *  Reset the SysTick, decrementing timer to it's maximum value and disable it.
+ *
+ *  This macro should leave the SysTick timer in a state that's ready for cycle
+ *  counting.
+ */
+#define JTEST_SYSTICK_RESET(systick_ptr)                    \
+    do                                                      \
+    {                                                       \
+        (systick_ptr)->CTRL = SysTick_CTRL_CLKSOURCE_Msk;   \
+                                                            \
+        (systick_ptr)->LOAD = JTEST_SYSTICK_INITIAL_VALUE;  \
+        (systick_ptr)->VAL  = JTEST_SYSTICK_INITIAL_VALUE;  \
+    } while (0)
+
+/**
+ *  Start the SysTick timer, sourced by the processor clock.
+ */
+#define JTEST_SYSTICK_START(systick_ptr)                    \
+    do                                                      \
+    {                                                       \
+        (systick_ptr)->CTRL =                               \
+            SysTick_CTRL_ENABLE_Msk |                       \
+            SysTick_CTRL_CLKSOURCE_Msk;                     \
+    } while (0)
+
+/**
+ *  Evaluate to the current value of the SysTick timer.
+ */
+#define JTEST_SYSTICK_VALUE(systick_ptr)                    \
+    ((systick_ptr)->VAL)
+           
+#endif /* _JTEST_SYSTICK_H_ */

resources/Camera_driver/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test.h

@@ -0,0 +1,100 @@
+#ifndef _JTEST_TEST_H_
+#define _JTEST_TEST_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include <stdint.h>
+#include "jtest_util.h"
+#include "jtest_test_ret.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Type Definitions */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  A struct which represents a Test in the JTEST framework.  This struct is
+ *  used to enable, run, and describe the test it represents.
+ */
+typedef struct JTEST_TEST_struct
+{
+    JTEST_TEST_RET_t ( * test_fn_ptr)(void); /**< Pointer to the test function. */
+    char   * test_fn_str;                    /**< Name of the test function */
+    char   * fut_str;           /**< Name of the function under test. */
+
+    /**
+     *  Flags that govern how the #JTEST_TEST_t behaves.
+     */
+    union {
+        struct {
+            unsigned enabled : 1;
+            unsigned unused  : 7;
+        } bits;
+        uint8_t byte;           /* Access all flags at once. */
+    } flags;
+    
+} JTEST_TEST_t;
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Assign a test function to the #JTEST_TEST_t struct.
+ */
+#define JTEST_TEST_SET_FN(jtest_test_ptr, fn_ptr)                   \
+    JTEST_SET_STRUCT_ATTRIBUTE(jtest_test_ptr, test_fn_ptr, fn_ptr)
+
+/**
+ *  Specify a function under test (FUT) for the #JTEST_TEST_t struct.
+ */
+#define JTEST_TEST_SET_FUT(jtest_test_ptr, str)                 \
+    JTEST_SET_STRUCT_ATTRIBUTE(jtest_test_ptr, fut_str, str)
+
+/* Macros concerning JTEST_TEST_t flags */
+/*--------------------------------------------------------------------------------*/
+
+#define JTEST_TEST_FLAG_SET 1 /**< Value of a set #JTEST_TEST_t flag. */
+#define JTEST_TEST_FLAG_CLR 0 /**< Value of a cleared #JTEST_TEST_t flag. */
+
+/**
+ *  Evaluate to the flag in #JTEST_TEST_t having flag_name.
+ */
+#define JTEST_TEST_FLAG(jtest_test_ptr, flag_name)  \
+    ((jtest_test_ptr)->flags.bits.flag_name)
+
+/**
+ *  Dispatch macro for setting and clearing #JTEST_TEST_t flags.
+ *
+ *  @param jtest_test_ptr Pointer to a #JTEST_TEST_t struct.
+ *  @param flag_name      Name of the flag to set in #JTEST_TEST_t.flags.bits
+ *  @param xxx            Vaid values: "SET" or "CLR"
+ *
+ *  @note This function depends on JTEST_TEST_FLAG_SET and JTEST_TEST_FLAG_CLR.
+ */
+#define JTEST_TEST_XXX_FLAG(jtest_test_ptr, flag_name, xxx)                  \
+    do                                                                       \
+    {                                                                        \
+        JTEST_TEST_FLAG(jtest_test_ptr, flag_name) = JTEST_TEST_FLAG_##xxx ; \
+    } while (0)
+
+/**
+ *  Specification of #JTEST_TEST_XXX_FLAG to set #JTEST_TEST_t flags.
+ */
+#define JTEST_TEST_SET_FLAG(jtest_test_ptr, flag_name)                       \
+    JTEST_TEST_XXX_FLAG(jtest_test_ptr, flag_name, SET)
+
+/**
+ *  Specification of #JTEST_TEST_XXX_FLAG to clear #JTEST_TEST_t flags.
+ */
+#define JTEST_TEST_CLR_FLAG(jtest_test_ptr, flag_name)                       \
+    JTEST_TEST_XXX_FLAG(jtest_test_ptr, flag_name, CLR)
+
+/**
+ *  Evaluate to true if the #JTEST_TEST_t is enabled.
+ */
+#define JTEST_TEST_IS_ENABLED(jtest_test_ptr)                           \
+    (JTEST_TEST_FLAG(jtest_test_ptr, enabled) == JTEST_TEST_FLAG_SET)
+
+#endif /* _JTEST_TEST_H_ */

resources/Camera_driver/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_call.h

@@ -0,0 +1,121 @@
+#ifndef _JTEST_TEST_CALL_H_
+#define _JTEST_TEST_CALL_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+#include "jtest_test.h"
+#include "jtest_test_define.h"
+#include "jtest_fw.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Exectute the test in the #JTEST_TEST_t struct associated with the identifier
+ *  test_fn and store the result in retval.
+ */
+#define JTEST_TEST_RUN(retval, test_fn)                                 \
+    do                                                                  \
+    {                                                                   \
+        JTEST_DUMP_STR("Test Name:\n");                                 \
+        JTEST_DUMP_STR(JTEST_TEST_STRUCT_NAME(test_fn).test_fn_str);    \
+        JTEST_DUMP_STR("Function Under Test:\n");                       \
+        JTEST_DUMP_STR(JTEST_TEST_STRUCT_NAME(test_fn).fut_str);        \
+        retval = JTEST_TEST_STRUCT_NAME(test_fn).test_fn_ptr();         \
+    } while (0)
+
+/**
+ *  Update the enclosing #JTEST_GROUP_t's pass/fail information based on
+ *  test_retval.
+ *
+ *  @param test_retval A #JTEST_TEST_RET_enum for the current test.
+ *
+ *  @warning Only use if #JTEST_TEST_t is called in the context of a
+ *  #JTEST_GROUP_t.
+ */
+#define JTEST_TEST_UPDATE_PARENT_GROUP_PF(test_retval)              \
+    do                                                              \
+    {                                                               \
+        /* Update enclosing JTEST_GROUP_t with pass/fail info */    \
+        if (test_retval == JTEST_TEST_PASSED)                       \
+        {                                                           \
+            JTEST_GROUP_INC_PASSED(JTEST_CURRENT_GROUP_PTR(), 1);   \
+        } else {                                                    \
+            JTEST_GROUP_INC_FAILED(JTEST_CURRENT_GROUP_PTR(), 1);   \
+        }                                                           \
+    } while (0)
+
+/**
+ *  Update the #JTEST_FW with pass/fail information based on test_retval.
+ *
+ *  @param test_retval A #JTEST_TEST_RET_enum for the current test.
+ */
+#define JTEST_TEST_UPDATE_FW_PF(test_retval)                        \
+    do                                                              \
+    {                                                               \
+        /* Update the JTEST_FW with pass/fail info */                \
+        if (test_retval == JTEST_TEST_PASSED)                       \
+        {                                                           \
+            JTEST_FW_INC_PASSED( 1);                                \
+        } else {                                                    \
+            JTEST_FW_INC_FAILED(1);                                 \
+        }                                                           \
+    } while (0)
+
+/**
+ *  Update the enclosing JTEST_GROUP_t's pass/fail information, or the
+ *  #JTEST_FW's if this test has no enclosing #JTEST_GROUP_t.
+ *
+ *  @param test_retval A #JTEST_TEST_RET_enum for the current test.
+ */
+#define JTEST_TEST_UPDATE_PARENT_GROUP_OR_FW_PF(test_retval)            \
+    do                                                                  \
+    {                                                                   \
+        /* Update pass-fail information */                              \
+        if (JTEST_CURRENT_GROUP_PTR() /* Non-null */)                    \
+        {                                                               \
+            JTEST_TEST_UPDATE_PARENT_GROUP_PF(test_retval);             \
+        } else {                                                        \
+            JTEST_TEST_UPDATE_FW_PF(test_retval);                       \
+        }                                                               \
+    } while (0)
+
+/**
+ *  Dump the results of the test to the Keil Debugger.
+ */
+#define JTEST_TEST_DUMP_RESULTS(test_retval)        \
+        do                                          \
+        {                                           \
+            if (test_retval == JTEST_TEST_PASSED)   \
+            {                                       \
+                JTEST_DUMP_STR("Test Passed\n");      \
+            } else {                                \
+                JTEST_DUMP_STR("Test Failed\n");      \
+            }                                       \
+        } while (0)
+
+/**
+ *  Call the #JTEST_TEST_t assocaited with the identifier test_fn.
+ */
+#define JTEST_TEST_CALL(test_fn)                                        \
+    do                                                                  \
+    {                                                                   \
+        if (JTEST_TEST_IS_ENABLED(&JTEST_TEST_STRUCT_NAME(test_fn)))    \
+        {                                                               \
+            /* Default to failure */                                    \
+            JTEST_TEST_RET_t __jtest_test_ret = JTEST_TEST_FAILED;      \
+                                                                        \
+            JTEST_ACT_TEST_START();                                     \
+            JTEST_TEST_RUN(__jtest_test_ret, test_fn);                  \
+                                                                        \
+            /* Update pass-fail information */                          \
+            JTEST_TEST_UPDATE_PARENT_GROUP_OR_FW_PF(__jtest_test_ret);  \
+                                                                        \
+            JTEST_TEST_DUMP_RESULTS(__jtest_test_ret);                  \
+            JTEST_ACT_TEST_END();                                       \
+        }                                                               \
+    } while (0)
+
+#endif /* _JTEST_TEST_CALL_H_ */

resources/Camera_driver/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_define.h

@@ -0,0 +1,133 @@
+#ifndef _JTEST_TEST_DEFINE_H_
+#define _JTEST_TEST_DEFINE_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "jtest_util.h"
+#include "jtest_define.h"
+#include "jtest_test.h"
+
+/* For defining macros with optional arguments */
+#include "opt_arg/opt_arg.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Prefix for all #JTEST_TEST_t structs.
+ */
+#define JTEST_TEST_STRUCT_NAME_PREFIX G_JTEST_TEST_STRUCT_
+
+/**
+ *  Define test template used by #JTEST_TEST_t tests.
+ */
+#define JTEST_TEST_FN_TEMPLATE(test_fn)                         \
+    JTEST_TEST_RET_t test_fn(void)
+
+#define JTEST_TEST_FN_PROTOTYPE JTEST_TEST_FN_TEMPLATE /**< Alias for
+                                                        * #JTEST_TEST_FN_TEMPLATE. */
+
+/**
+ *  Evaluate to the name of the #JTEST_TEST_t struct associated with test_fn.
+ */
+#define JTEST_TEST_STRUCT_NAME(test_fn)                         \
+    JTEST_STRUCT_NAME(JTEST_TEST_STRUCT_NAME_PREFIX, test_fn)
+
+/**
+ *  Define a #JTEST_TEST_t struct based on the given test_fn.
+ */
+#define JTEST_TEST_DEFINE_STRUCT(test_fn)                   \
+    JTEST_DEFINE_STRUCT(JTEST_TEST_t,                       \
+                        JTEST_TEST_STRUCT_NAME(test_fn))
+
+/**
+ *  Declare a #JTEST_TEST_t struct based on the given test_fn.
+ */
+#define JTEST_TEST_DECLARE_STRUCT(test_fn)      \
+    JTEST_DECLARE_STRUCT(JTEST_TEST_DEFINE_STRUCT(test_fn))
+
+/**
+ *  Contents needed to initialize a JTEST_TEST_t struct.
+ */
+#define JTEST_TEST_STRUCT_INIT(test_fn, fut, enable)    \
+    test_fn,                                            \
+        STR_NL(test_fn),                                   \
+        STR_NL(fut),                                       \
+    {                                                   \
+        {                                               \
+            enable,                                     \
+                0                                       \
+        }                                               \
+    }                                                   \
+        
+
+/**
+ *  Initialize the contents of a #JTEST_TEST_t struct.
+ */
+#define JTEST_TEST_INIT(test_fn, fut, enable)              \
+    JTEST_TEST_DEFINE_STRUCT(test_fn) = {                  \
+        JTEST_TEST_STRUCT_INIT(test_fn, fut, enable)       \
+    }
+
+/* Test Definition Macro */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Define a #JTEST_TEST_t object and a test function.
+ */
+#define _JTEST_DEFINE_TEST(test_fn, fut, enable)           \
+    JTEST_TEST_FN_PROTOTYPE(test_fn);                      \
+    JTEST_TEST_INIT(test_fn, fut, enable);                 \
+    JTEST_TEST_FN_PROTOTYPE(test_fn) /* Notice the lacking semicolon */
+
+/**
+ *  Declare a #JTEST_TEST_t object and a test function prototype.
+ */
+#define JTEST_DECLARE_TEST(test_fn)                                     \
+    JTEST_TEST_FN_PROTOTYPE(test_fn);                                   \
+    JTEST_TEST_DECLARE_STRUCT(test_fn) /* Note the lacking semicolon */
+
+/*--------------------------------------------------------------------------------*/
+/* Macros with optional arguments */
+/*--------------------------------------------------------------------------------*/
+
+/* Top-level Interface */
+#define JTEST_DEFINE_TEST(...)                             \
+    JTEST_DEFINE_TEST_(PP_NARG(__VA_ARGS__), ##__VA_ARGS__)
+
+/* Dispatch Macro*/
+#define JTEST_DEFINE_TEST_(N, ...)                         \
+    SPLICE(JTEST_DEFINE_TEST_, N)(__VA_ARGS__)
+
+/* Default Arguments */
+#define JTEST_DEFINE_TEST_DEFAULT_FUT /* Blank */
+#define JTEST_DEFINE_TEST_DEFAULT_ENABLE                   \
+    JTEST_TRUE                                 /* Tests enabled by
+                                                * default. */ 
+
+/* Dispatch Cases*/
+#define JTEST_DEFINE_TEST_1(_1)                            \
+    _JTEST_DEFINE_TEST(                                    \
+        _1,                                                \
+        JTEST_DEFINE_TEST_DEFAULT_FUT,                     \
+        JTEST_DEFINE_TEST_DEFAULT_ENABLE                   \
+        )
+
+#define JTEST_DEFINE_TEST_2(_1, _2)                        \
+    _JTEST_DEFINE_TEST(                                    \
+        _1,                                                \
+        _2,                                                \
+        JTEST_DEFINE_TEST_DEFAULT_ENABLE                   \
+        )
+
+#define JTEST_DEFINE_TEST_3(_1, _2, _3)                    \
+    _JTEST_DEFINE_TEST(                                    \
+        _1,                                                \
+        _2,                                                \
+        _3                                                 \
+        )
+
+#endif /* _JTEST_TEST_DEFINE_H_ */

resources/Camera_driver/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_ret.h

@@ -0,0 +1,17 @@
+#ifndef _JTEST_TEST_RET_H_
+#define _JTEST_TEST_RET_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Type Definitions */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Values a #JTEST_TEST_t can return.
+ */
+typedef enum JTEST_TEST_RET_enum
+{
+    JTEST_TEST_PASSED,
+    JTEST_TEST_FAILED
+} JTEST_TEST_RET_t;
+
+#endif /* _JTEST_TEST_RET_H_ */

resources/Camera_driver/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_util.h

@@ -0,0 +1,27 @@
+#ifndef _JTEST_UTIL_H_
+#define _JTEST_UTIL_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "util/util.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/* Define boolean values for the framework. */
+#define JTEST_TRUE  1           /**< Value used for TRUE in JTEST. */
+#define JTEST_FALSE 0           /**< Value used for FALSE in JTEST. */
+
+/**
+ *  Set the value of the attribute in the struct to by struct_ptr to value.
+ */
+#define JTEST_SET_STRUCT_ATTRIBUTE(struct_ptr, attribute, value)    \
+    do                                                              \
+    {                                                               \
+        (struct_ptr)->attribute = (value);                          \
+    } while (0)
+
+#endif /* _JTEST_UTIL_H_ */

resources/Camera_driver/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/opt_arg.h

@@ -0,0 +1,15 @@
+#ifndef _OPT_ARG_H_
+#define _OPT_ARG_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "pp_narg.h"
+#include "splice.h"
+
+/* If you are Joseph Jaoudi, you have a snippet which expands into an
+   example. If you are not Joseph, but possess his code, study the examples. If
+   you have no examples, turn back contact Joseph. */
+
+#endif /* _OPT_ARG_H_ */

resources/Camera_driver/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/pp_narg.h

@@ -0,0 +1,25 @@
+#ifndef _PP_NARG_H_
+#define _PP_NARG_H_
+
+#define PP_NARG(...)                                      \
+    PP_NARG_(__VA_ARGS__,PP_RSEQ_N())
+#define PP_NARG_(...)                                     \
+    PP_ARG_N(__VA_ARGS__)
+#define PP_ARG_N(                                         \
+                 _1, _2, _3, _4, _5, _6, _7, _8, _9,_10,  \
+                 _11,_12,_13,_14,_15,_16,_17,_18,_19,_20, \
+                 _21,_22,_23,_24,_25,_26,_27,_28,_29,_30, \
+                 _31,_32,_33,_34,_35,_36,_37,_38,_39,_40, \
+                 _41,_42,_43,_44,_45,_46,_47,_48,_49,_50, \
+                 _51,_52,_53,_54,_55,_56,_57,_58,_59,_60, \
+                 _61,_62,_63,N,...) N
+#define PP_RSEQ_N()                                       \
+    63,62,61,60,                                          \
+        59,58,57,56,55,54,53,52,51,50,                    \
+        49,48,47,46,45,44,43,42,41,40,                    \
+        39,38,37,36,35,34,33,32,31,30,                    \
+        29,28,27,26,25,24,23,22,21,20,                    \
+        19,18,17,16,15,14,13,12,11,10,                    \
+        9,8,7,6,5,4,3,2,1,0
+
+#endif /* _PP_NARG_H_ */