EPS: initial parts separation and group labeling

Solar_module_XY
Petr Malanik 3 years ago
parent e57654efa0
commit 260fe3d954

File diff suppressed because it is too large Load Diff

@ -1,6 +1,6 @@
{
"board": {
"active_layer": 44,
"active_layer": 0,
"active_layer_preset": "",
"auto_track_width": true,
"hidden_nets": [],
@ -62,7 +62,7 @@
35,
36
],
"visible_layers": "ffcffff_ffffffff",
"visible_layers": "7fcffff_80000007",
"zone_display_mode": 1
},
"meta": {

@ -101,23 +101,27 @@
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_clearance": 0.15,
"min_copper_edge_clearance": 0.0,
"min_hole_clearance": 0.0,
"min_hole_to_hole": 0.25,
"min_hole_to_hole": 0.3,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_silk_clearance": 0.0,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.19999999999999998,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.39999999999999997,
"min_through_hole_diameter": 0.19999999999999998,
"min_track_width": 0.15,
"min_via_annular_width": 0.125,
"min_via_diameter": 0.44999999999999996,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0,
"use_height_for_length_calcs": true
},
"track_widths": [
0.0
0.0,
0.15,
0.25,
0.5,
1.0
],
"via_dimensions": [
{
@ -356,14 +360,14 @@
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"microvia_diameter": 0.5,
"microvia_drill": 0.2,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.15,
"via_diameter": 0.8,
"via_drill": 0.4,
"via_diameter": 0.5,
"via_drill": 0.2,
"wire_width": 6.0
}
],

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