66 Commits
Author SHA1 Message Date
Štěpán Rydlo acc8a9dad4 COMM: Revert "COMM: Create Gerber files"
This reverts commit a981cda0f4.
2022-08-31 14:12:38 +02:00
Štěpán Rydlo 3f217bffca COMM: Create Gerber files 2022-08-31 14:12:38 +02:00
Štěpán Rydlo a0e04ff695 COMM: Change 3V3 path 2022-08-31 14:12:38 +02:00
Štěpán Rydlo 8ab55f614c COMM: Edit infil on stack conector for GROUND 2022-08-31 14:12:38 +02:00
Štěpán Rydlo eef2911555 COMM: Add heat vias 2022-08-31 14:12:37 +02:00
Štěpán Rydlo b3f827c8c8 COMM: Upload changes, after close file 2022-08-31 14:12:37 +02:00
Štěpán Rydlo 11c2653773 COMM: Remove autosaveFile. Reupload last edit 2022-08-31 14:12:37 +02:00
Štěpán Rydlo 2acb56bee4 COMM: Change of some VIAS and path 2022-08-31 14:12:37 +02:00
Štěpán Rydlo c795bd17a7 COMM: Add logo and vias 2022-08-31 14:12:36 +02:00
Štěpán Rydlo 06323329bc COMM: Change connectors header to horizontal. 2022-08-31 14:12:36 +02:00
Štěpán Rydlo 0bffb251e4 COMM: Change package for impendance adjustment resistor of RS-485 2022-08-31 14:12:36 +02:00
Štěpán Rydlo 990fb34c16 COMM: Change position of decloupling capacitor to transmiter chip (repair) 2022-08-31 14:12:36 +02:00
Štěpán Rydlo 969d393941 COMM: Repair next paths connection to via or pad 2022-08-31 14:12:36 +02:00
Štěpán Rydlo 7ba8f4db97 COMM: Change path connections to pads and vias 2022-08-31 14:12:35 +02:00
Štěpán Rydlo 69a3a0c95d COMM: Change paths under communication modules 2022-08-31 14:12:35 +02:00
Štěpán Rydlo 8fb655c931 COMM: rebuild openLST 2022-08-31 14:12:35 +02:00
Štěpán Rydlo f09e8e95e7 COMM: Change CAN to symetric paths 2022-08-31 14:12:35 +02:00
Štěpán Rydlo 7b638ed5af COMM: change CAN and reapair trim path 2022-08-31 14:12:28 +02:00
Štěpán Rydlo cd087524e3 COMM: Change paths uder GPS module 2022-08-31 14:12:28 +02:00
Štěpán Rydlo d1ace3c00e COMM: Change position of path from antenas 2022-08-31 14:12:21 +02:00
Štěpán Rydlo 901011cc9e COMM: Saved repair 2022-08-31 14:12:21 +02:00
Štěpán Rydlo ecb7f074cf COMM: Repair all errors and warnings 2022-08-31 14:12:21 +02:00
Štěpán Rydlo ddd6f2af58 COMM: Change trimmer 2022-08-31 14:12:20 +02:00
Štěpán Rydlo 282ad9f1ac COMM: Add label to stack connector. 2022-08-31 14:12:20 +02:00
Štěpán Rydlo 3d039213c1 COMM: edit STM programing connector 2022-08-31 14:12:20 +02:00
Štěpán Rydlo da936339a3 COMM: Edit label to camera connector 2022-08-31 14:12:19 +02:00
Štěpán Rydlo 231d70dbca COMM: Edit connector to STM32 USB debug, position and labels 2022-08-31 14:12:19 +02:00
Štěpán Rydlo db2ed61444 COMM: add label to antena connectoir 2022-08-31 14:12:19 +02:00
Štěpán Rydlo eddfca2030 COMM: Change position and label to LST_debug connector 2022-08-31 14:12:19 +02:00
Štěpán Rydlo f4bc2e54b5 COMM: Edit J2 connector for LST programing 2022-08-31 14:12:19 +02:00
Štěpán Rydlo e3561116fb COMM: add description to USB pinout 2022-08-31 14:12:18 +02:00
Štěpán Rydlo 3818a4eb28 COMM: change USB port to STM 2022-08-31 14:12:18 +02:00
Petr MalanikandŠtěpán Rydlo 8855583bf8 COMM: Fix border alignment of zones, add ground planes to inner layers 2022-08-31 14:12:12 +02:00
Štěpán Rydlo 89103b917c COMM: Finish of PCB for control 2022-08-31 14:11:57 +02:00
Štěpán Rydlo 87b4c7f870 COMM: Conector description 2022-08-31 14:11:49 +02:00
Štěpán Rydlo 6d9dcf2122 COMM: Change connector 2022-08-31 14:11:41 +02:00
Štěpán Rydlo 830d4e2c5c COMM: Repair errors. Only error in default width. 2022-08-31 14:11:33 +02:00
Štěpán Rydlo edfc9215d7 COMM: Revert "Finish routing. Have to repair errors."
This reverts commit 45ad17769d.
2022-08-31 14:11:25 +02:00
Štěpán Rydlo 218135b7d1 COMM: finish routing of communicatnion board 2022-08-31 14:11:19 +02:00
Štěpán Rydlo 4bfd769052 COMM: Finish routing. Have to repair errors. 2022-08-31 14:11:14 +02:00
Štěpán Rydlo 3b6c325d6b COMM: Next version of pcb. Added camera switch 2022-08-31 14:11:09 +02:00
Štěpán Rydlo 66f4716a33 COMM: Complete power share and connection to stack connector. Change gps module and impedances paths 2022-08-31 14:11:03 +02:00
Štěpán Rydlo 1c2a0b8cb5 COMM: Complete power supply share and convertor 2022-08-31 14:10:56 +02:00
Štěpán Rydlo 78057964eb COMM: Place power supply share, to the board 2022-08-31 14:10:38 +02:00
Štěpán Rydlo 37d71fe987 COMM: GPS and nRF placed plus 5V powershare sketch 2022-08-31 14:10:31 +02:00
Štěpán Rydlo d77aee649d COMM: Rework camera connector mounting to MCU 2022-08-31 14:10:18 +02:00
Štěpán Rydlo 41ac366142 COMM: Add table of possible connetion camera or qspi 2022-08-31 14:09:43 +02:00
Štěpán Rydlo 7122abbbb4 COMM: Add Camera connector, to SPI and I2C 2022-08-31 14:09:22 +02:00
Štěpán Rydlo 1dcd42c4e4 COMM: Edit transistor for enable signal coil in 3V6 2022-08-31 14:09:13 +02:00
Štěpán Rydlo 7872bde2e1 COMM: Repair Mosfet and capacitors 2022-08-31 14:09:05 +02:00
Štěpán Rydlo ba46e36520 COMM: Edit all notes after next review 2022-08-31 14:08:40 +02:00
Petr MalanikandŠtěpán Rydlo 07f234b367 COMM: Review - round 4 2022-08-31 14:08:08 +02:00
Štěpán Rydlo a88c93c9df COMM: Finish implemention of all notes for next control. 2022-08-31 13:59:48 +02:00
Petr MalanikandŠtěpán Rydlo e9dc1537c3 COMM: Review - round 3 2022-08-31 13:59:16 +02:00
Štěpán RydloandŠtěpán Rydlo c9d8955cf6 COMM: Finish next changes after review 2022-08-31 13:59:04 +02:00
Petr MalanikandŠtěpán Rydlo c7a291d89b COMM: Review - round 2 2022-08-31 13:58:26 +02:00
Štěpán RydloandŠtěpán Rydlo ee542cd0a7 COMM: Finish communication to next review 2022-08-31 13:57:53 +02:00
Štěpán RydloandŠtěpán Rydlo 3129a41203 COMM: Edit VDDUSB to voltage divider. Change 3,6V boost, buck 2022-08-31 13:56:42 +02:00
Štěpán RydloandŠtěpán Rydlo 8764cab52e COMM: Edit 3,6V enable for openLST, USB interface. 2022-08-31 13:56:10 +02:00
Štěpán RydloandŠtěpán Rydlo 22407fb07e COMM: Edit review notes. 2022-08-31 13:55:44 +02:00
Petr MalanikandŠtěpán Rydlo 5f6571cd36 COMM: Review - round 1 2022-08-31 13:40:19 +02:00
Štěpán RydloandŠtěpán Rydlo 1ece258700 COMM: Edit comm module. Rework all notes 2022-08-31 13:33:14 +02:00
Štěpán RydloandŠtěpán Rydlo 385b613282 COMM: Complete schematic of Communication 2022-08-31 13:31:32 +02:00
Štěpán RydloandŠtěpán Rydlo 7a87bed511 COMM: Add nRF to communication. Add powersupply take for 3.3V. Missing MCU connection 2022-08-31 13:30:43 +02:00
Štěpán RydloandŠtěpán Rydlo cd2c48d1fe COMM: Create possibilty of switching between two battery 2022-08-31 13:30:16 +02:00
irydlo 75c763b78d COMM: Create schematic first part of comm module 2021-09-06 08:47:45 +02:00
1359 changed files with 278610 additions and 1817027 deletions
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About_me.md About_me.md
modules/Communication/comm-backups
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"orig_nbformat": 4,
"kernelspec": {
"name": "python3",
"display_name": "Python 3.9.7 64-bit"
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"interpreter": {
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{
"cell_type": "code",
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"source": [
"# Battery voltage comparator with histerezes\r\n",
"\r\n",
"\r\n",
"supply_voltage = 1.6\r\n",
"reference_voltage = 2\r\n",
"\r\n",
"R1 = 50000\r\n",
"R2 = 330000\r\n",
"\r\n",
"Vin_High = R1 * (reference_voltage / R2) + reference_voltage \r\n",
"\r\n",
"print(\"Voltage switch to high: {}V\".format(round(Vin_High,2)))\r\n",
"\r\n",
"Vin_Low = (reference_voltage*(R1+R2) - supply_voltage * R1) / R2\r\n",
"\r\n",
"print(\"Voltage switch to low: {}V\".format(round(Vin_Low,2)))\r\n",
"\r\n",
"Vin_delta = supply_voltage * (R1/R2)\r\n",
"\r\n",
"print(\"Voltage delta: {}V\".format(round(Vin_delta,2)))\r\n"
],
"outputs": [
{
"output_type": "stream",
"name": "stdout",
"text": [
"Voltage switch to high: 1.15V\n",
"Voltage switch to low: 0.91V\n",
"Voltage delta: 0.24V\n"
]
}
],
"metadata": {}
}
]
}
+670
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File diff suppressed because it is too large Load Diff
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File diff suppressed because it is too large Load Diff
@@ -1,8 +1,8 @@
{ {
"board": { "board": {
"active_layer": 36, "active_layer": 31,
"active_layer_preset": "", "active_layer_preset": "",
"auto_track_width": false, "auto_track_width": true,
"hidden_nets": [], "hidden_nets": [],
"high_contrast_mode": 1, "high_contrast_mode": 1,
"net_color_mode": 1, "net_color_mode": 1,
@@ -36,7 +36,6 @@
8, 8,
9, 9,
10, 10,
11,
12, 12,
13, 13,
14, 14,
@@ -62,11 +61,11 @@
35, 35,
36 36
], ],
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"zone_display_mode": 0 "zone_display_mode": 0
}, },
"meta": { "meta": {
"filename": "Sun_sensor.kicad_prl", "filename": "comm.kicad_prl",
"version": 3 "version": 3
}, },
"project": { "project": {
@@ -33,9 +33,9 @@
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"other_text_upright": false, "other_text_upright": false,
"pads": { "pads": {
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"height": 1.524, "height": 0.22,
"width": 1.524 "width": 0.22
}, },
"silk_line_width": 0.15, "silk_line_width": 0.15,
"silk_text_italic": false, "silk_text_italic": false,
@@ -45,7 +45,7 @@
"silk_text_upright": false, "silk_text_upright": false,
"zones": { "zones": {
"45_degree_only": false, "45_degree_only": false,
"min_clearance": 0.254 "min_clearance": 0.19999999999999998
} }
}, },
"diff_pair_dimensions": [ "diff_pair_dimensions": [
@@ -53,6 +53,11 @@
"gap": 0.0, "gap": 0.0,
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"width": 0.0 "width": 0.0
},
{
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], ],
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@@ -103,29 +108,31 @@
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"allow_microvias": false, "allow_microvias": false,
"max_error": 0.005, "max_error": 0.005,
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"min_hole_clearance": 0.19999999999999998, "min_hole_clearance": 0.25,
"min_hole_to_hole": 0.3, "min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998, "min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999, "min_microvia_drill": 0.09999999999999999,
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"min_through_hole_diameter": 0.19999999999999998, "min_through_hole_diameter": 0.3,
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"min_via_annular_width": 0.125, "min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.44999999999999996, "min_via_diameter": 0.39999999999999997,
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"solder_mask_min_width": 0.0, "solder_mask_min_width": 0.0,
"use_height_for_length_calcs": true "use_height_for_length_calcs": true
}, },
"track_widths": [ "track_widths": [
0.0, 0.0,
0.1,
0.15, 0.15,
0.2,
0.25, 0.25,
0.5, 0.3,
1.0, 0.35,
1.5, 0.4,
2.0 1.0
], ],
"via_dimensions": [ "via_dimensions": [
{ {
@@ -352,26 +359,26 @@
"pinned_symbol_libs": [] "pinned_symbol_libs": []
}, },
"meta": { "meta": {
"filename": "Sun_sensor.kicad_pro", "filename": "comm.kicad_pro",
"version": 1 "version": 1
}, },
"net_settings": { "net_settings": {
"classes": [ "classes": [
{ {
"bus_width": 12.0, "bus_width": 12.0,
"clearance": 0.15, "clearance": 0.2,
"diff_pair_gap": 0.25, "diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25, "diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2, "diff_pair_width": 0.15,
"line_style": 0, "line_style": 0,
"microvia_diameter": 0.45, "microvia_diameter": 0.3,
"microvia_drill": 0.2, "microvia_drill": 0.1,
"name": "Default", "name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)", "pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)", "schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.15, "track_width": 0.25,
"via_diameter": 0.45, "via_diameter": 0.8,
"via_drill": 0.2, "via_drill": 0.4,
"wire_width": 6.0 "wire_width": 6.0
} }
], ],
@@ -386,16 +393,19 @@
"idf": "", "idf": "",
"netlist": "", "netlist": "",
"specctra_dsn": "", "specctra_dsn": "",
"step": "Sun_sensor.step", "step": "",
"vrml": "" "vrml": ""
}, },
"page_layout_descr_file": "/home/petr/work/butcube/resources/kicad_page_layout.kicad_wks" "page_layout_descr_file": ""
}, },
"schematic": { "schematic": {
"annotate_start_num": 0, "annotate_start_num": 0,
"drawing": { "drawing": {
"default_bus_thickness": 12.0,
"default_junction_size": 40.0,
"default_line_thickness": 6.0, "default_line_thickness": 6.0,
"default_text_size": 50.0, "default_text_size": 50.0,
"default_wire_thickness": 6.0,
"field_names": [], "field_names": [],
"intersheets_ref_own_page": false, "intersheets_ref_own_page": false,
"intersheets_ref_prefix": "", "intersheets_ref_prefix": "",
@@ -422,7 +432,7 @@
"model_mode": 0, "model_mode": 0,
"workbook_filename": "" "workbook_filename": ""
}, },
"page_layout_descr_file": "/home/petr/work/butcube/resources/kicad_page_layout.kicad_wks", "page_layout_descr_file": "",
"plot_directory": "", "plot_directory": "",
"spice_adjust_passive_values": false, "spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"", "spice_external_command": "spice \"%I\"",
@@ -431,8 +441,48 @@
}, },
"sheets": [ "sheets": [
[ [
"b4fcae78-0ce7-4618-9b55-3d67c0b38940", "b0365847-75b4-4551-b23a-00058264c694",
"" ""
],
[
"829b2795-9702-4633-a078-e2998d6d9402",
"OpenLST (Beacon)"
],
[
"3006f49f-d72b-4219-8dea-bda42cf88e84",
"Stack Connector"
],
[
"135894dc-6710-4561-8073-567533e9f424",
"GPS Module"
],
[
"a345038c-0e2c-4410-9183-a80a047c8766",
"nRF Transceiver"
],
[
"81a5172c-b171-400d-8856-41d6e486bdd1",
"MCU"
],
[
"5d794243-d9db-4c8e-aa14-90dff0141470",
"3V3 power share"
],
[
"d3a682e4-d5b0-4377-8f5c-e0ae4cebf08d",
"Power Convertor"
],
[
"1e3f6e69-339a-4a82-8e4d-44c2adb747fb",
"camera"
],
[
"267a91a1-f60f-4e4e-a455-eed28f022043",
"VBAT1"
],
[
"a161eaab-f432-4250-8567-12738a9776f7",
"5V power share"
] ]
], ],
"text_variables": {} "text_variables": {}
File diff suppressed because it is too large Load Diff
File diff suppressed because it is too large Load Diff
@@ -0,0 +1,2 @@
Default True 2.0 3
False True
File diff suppressed because it is too large Load Diff
+30
View File
@@ -0,0 +1,30 @@
Power consuption:
3V3
PowerDelivery 0,003 2 0,006
GPS neo-q8 0,1 1 0,1
GPS zesil 0,06 1 0,06
nRF receive 0,0113 1 0,0113
nRF transmit 0,0123 1 0,0123
MCU 0,28 1 0,28
CC11111 0,037 1 0,037
ToTAL MAX 3V3 0,5066A
5V
Voltage divider to OpenLST
VBat
RFFM6406 Voltage 3V6 max current 1,2A
Board:
Gatema Typ desky ISOLA IS400, 1000. tlouťka, 18um CU folie.
Dk 4.39
Compute path width:
3V3 => 0,3
VBat and 3V6 => 0,8
5V => 0,3
50Ohm impedances 0,35mm
dataTrace -> 0.1/0.15mm
File diff suppressed because it is too large Load Diff
File diff suppressed because it is too large Load Diff
File diff suppressed because it is too large Load Diff
File diff suppressed because it is too large Load Diff
File diff suppressed because it is too large Load Diff
+104
View File
@@ -0,0 +1,104 @@
03-17 20:07:41 replicate_layout.action_replicate_layout 305:Plugin executed on: 'win32'
03-17 20:07:41 replicate_layout.action_replicate_layout 306:Plugin executed with python version: '3.9.6 (default, Sep 27 2021, 21:15:11) [MSC v.1929 64 bit (AMD64)]'
03-17 20:07:41 replicate_layout.action_replicate_layout 307:KiCad build version: (6.0.0)
03-17 20:07:41 replicate_layout.action_replicate_layout 308:Replicate layout plugin version: 77 started
03-17 20:07:41 replicate_layout.action_replicate_layout 339:Preparing replicator with U3 as a reference
03-17 20:07:41 replicate_layout.replicatelayout 141:getting a list of all footprints on board
03-17 20:07:41 replicate_layout.replicatelayout 162:total modules:239
03-17 20:07:41 replicate_layout.action_replicate_layout 366:source anchor footprint is 'U3'
Located on:['', '3V3 power share']
With filenames:['comm.kicad_sch', 'powerShare_sch.kicad_sch']
With sheet_id:['', '3V3 power share']
03-17 20:07:41 replicate_layout.action_replicate_layout 371:Corresponding footprints are
[('U19', ['', '5V power share']), ('U18', ['', 'Power Convertor', 'VBAT1']), ('U3', ['', '3V3 power share'])]
03-17 20:07:41 replicate_layout.action_replicate_layout 384:Showing dialog
03-17 20:07:41 replicate_layout.action_replicate_layout 388:Pcbnew position: wx.Point(2553, 0)
03-17 20:07:41 replicate_layout.action_replicate_layout 394:Display 0: wx.Rect(-1920, 351, 1920, 1080)
03-17 20:07:41 replicate_layout.action_replicate_layout 394:Display 1: wx.Rect(0, 0, 5120, 1440)
03-17 20:07:41 replicate_layout.action_replicate_layout 398:Toolbar position: wx.Point(4898, 128)
03-17 20:07:41 replicate_layout.action_replicate_layout 405:Dialog position: wx.Point(4585, 128)
03-17 20:07:46 replicate_layout.replicatelayout 177:construcing a list of sheets suitable for replication on level:'3V3 power share', file:'powerShare_sch.kicad_sch'
03-17 20:07:46 replicate_layout.replicatelayout 184:Source sheet path up to the level:['', '3V3 power share']
03-17 20:07:46 replicate_layout.replicatelayout 188:Footprints on the sheets:
['U19', 'U18', 'U3']
03-17 20:07:46 replicate_layout.replicatelayout 191:Footprints raw sheet ids:
['/a161eaab-f432-4250-8567-12738a9776f7/dd4673e5-88b8-4bb8-94af-40b6837b93f2', '/d3a682e4-d5b0-4377-8f5c-e0ae4cebf08d/267a91a1-f60f-4e4e-a455-eed28f022043/dd4673e5-88b8-4bb8-94af-40b6837b93f2', '/5d794243-d9db-4c8e-aa14-90dff0141470/dd4673e5-88b8-4bb8-94af-40b6837b93f2']
03-17 20:07:46 replicate_layout.replicatelayout 207:All sheets to replicate:
[['', '5V power share'], ['', 'Power Convertor', 'VBAT1'], ['', '3V3 power share']]
03-17 20:07:46 replicate_layout.replicatelayout 212:All sheets to replicate sorted:
[['', '3V3 power share'], ['', '5V power share'], ['', 'Power Convertor', 'VBAT1']]
03-17 20:07:46 replicate_layout.replicatelayout 218:All sheets to replicate sorted and without source sheet:
[['', '5V power share'], ['', 'Power Convertor', 'VBAT1']]
03-17 20:07:50 replicate_layout.replicatelayout 177:construcing a list of sheets suitable for replication on level:'', file:'comm.kicad_sch'
03-17 20:07:50 replicate_layout.replicatelayout 184:Source sheet path up to the level:['']
03-17 20:07:50 replicate_layout.replicatelayout 188:Footprints on the sheets:
['U19', 'U18', 'U3']
03-17 20:07:50 replicate_layout.replicatelayout 191:Footprints raw sheet ids:
['/a161eaab-f432-4250-8567-12738a9776f7/dd4673e5-88b8-4bb8-94af-40b6837b93f2', '/d3a682e4-d5b0-4377-8f5c-e0ae4cebf08d/267a91a1-f60f-4e4e-a455-eed28f022043/dd4673e5-88b8-4bb8-94af-40b6837b93f2', '/5d794243-d9db-4c8e-aa14-90dff0141470/dd4673e5-88b8-4bb8-94af-40b6837b93f2']
03-17 20:07:50 replicate_layout.replicatelayout 207:All sheets to replicate:
[[''], [''], ['']]
03-17 20:07:50 replicate_layout.replicatelayout 212:All sheets to replicate sorted:
[['']]
03-17 20:07:50 replicate_layout.replicatelayout 218:All sheets to replicate sorted and without source sheet:
[]
03-17 20:07:51 replicate_layout.replicatelayout 177:construcing a list of sheets suitable for replication on level:'3V3 power share', file:'powerShare_sch.kicad_sch'
03-17 20:07:51 replicate_layout.replicatelayout 184:Source sheet path up to the level:['', '3V3 power share']
03-17 20:07:51 replicate_layout.replicatelayout 188:Footprints on the sheets:
['U19', 'U18', 'U3']
03-17 20:07:51 replicate_layout.replicatelayout 191:Footprints raw sheet ids:
['/a161eaab-f432-4250-8567-12738a9776f7/dd4673e5-88b8-4bb8-94af-40b6837b93f2', '/d3a682e4-d5b0-4377-8f5c-e0ae4cebf08d/267a91a1-f60f-4e4e-a455-eed28f022043/dd4673e5-88b8-4bb8-94af-40b6837b93f2', '/5d794243-d9db-4c8e-aa14-90dff0141470/dd4673e5-88b8-4bb8-94af-40b6837b93f2']
03-17 20:07:51 replicate_layout.replicatelayout 207:All sheets to replicate:
[['', '5V power share'], ['', 'Power Convertor', 'VBAT1'], ['', '3V3 power share']]
03-17 20:07:51 replicate_layout.replicatelayout 212:All sheets to replicate sorted:
[['', '3V3 power share'], ['', '5V power share'], ['', 'Power Convertor', 'VBAT1']]
03-17 20:07:51 replicate_layout.replicatelayout 218:All sheets to replicate sorted and without source sheet:
[['', '5V power share'], ['', 'Power Convertor', 'VBAT1']]
03-17 20:07:55 replicate_layout.replicatelayout 177:construcing a list of sheets suitable for replication on level:'3V3 power share', file:'powerShare_sch.kicad_sch'
03-17 20:07:55 replicate_layout.replicatelayout 184:Source sheet path up to the level:['', '3V3 power share']
03-17 20:07:55 replicate_layout.replicatelayout 188:Footprints on the sheets:
['U19', 'U18', 'U3']
03-17 20:07:55 replicate_layout.replicatelayout 191:Footprints raw sheet ids:
['/a161eaab-f432-4250-8567-12738a9776f7/dd4673e5-88b8-4bb8-94af-40b6837b93f2', '/d3a682e4-d5b0-4377-8f5c-e0ae4cebf08d/267a91a1-f60f-4e4e-a455-eed28f022043/dd4673e5-88b8-4bb8-94af-40b6837b93f2', '/5d794243-d9db-4c8e-aa14-90dff0141470/dd4673e5-88b8-4bb8-94af-40b6837b93f2']
03-17 20:07:55 replicate_layout.replicatelayout 207:All sheets to replicate:
[['', '5V power share'], ['', 'Power Convertor', 'VBAT1'], ['', '3V3 power share']]
03-17 20:07:55 replicate_layout.replicatelayout 212:All sheets to replicate sorted:
[['', '3V3 power share'], ['', '5V power share'], ['', 'Power Convertor', 'VBAT1']]
03-17 20:07:55 replicate_layout.replicatelayout 218:All sheets to replicate sorted and without source sheet:
[['', '5V power share'], ['', 'Power Convertor', 'VBAT1']]
03-17 20:07:55 replicate_layout.action_replicate_layout 179:Replicating layout
03-17 20:07:55 replicate_layout.replicatelayout 927:Starting replication of sheets: [['', '5V power share'], ['', 'Power Convertor', 'VBAT1']]
on level: ['', '3V3 power share']
with tracks=True, zone=True, text=True, containing=True, remove=False, locked=False
03-17 20:07:55 root 261:updating GUI message: 'Preparing for replication'
03-17 20:07:55 root 266:updating GUI with: 0
03-17 20:07:55 replicate_layout.replicatelayout 491:Getting the list of source footprints
03-17 20:07:55 replicate_layout.replicatelayout 495:Getting the list of all the remaining footprints
03-17 20:07:55 replicate_layout.replicatelayout 499:Getting nets local to source footprints
03-17 20:07:55 replicate_layout.replicatelayout 503:Getting source bounding box
03-17 20:07:55 replicate_layout.replicatelayout 507:Getting source tracks
03-17 20:07:55 replicate_layout.replicatelayout 511:Getting source zones
03-17 20:07:55 replicate_layout.replicatelayout 515:Getting source text items
03-17 20:07:55 replicate_layout.replicatelayout 519:Getting source text items
03-17 20:07:55 root 261:updating GUI message: 'Replicating footprints'
03-17 20:07:55 replicate_layout.replicatelayout 525:Replicating footprints
03-17 20:07:55 replicate_layout.replicatelayout 531:Replicating footprints on sheet ['', '5V power share']
03-17 20:07:55 root 266:updating GUI with: 9
03-17 20:07:55 replicate_layout.replicatelayout 531:Replicating footprints on sheet ['', 'Power Convertor', 'VBAT1']
03-17 20:07:55 root 261:updating GUI message: 'Replicating tracks'
03-17 20:07:55 replicate_layout.replicatelayout 657:Replicating tracks
03-17 20:07:55 replicate_layout.replicatelayout 663:Replicating tracks on sheet ['', '5V power share']
03-17 20:07:55 replicate_layout.replicatelayout 663:Replicating tracks on sheet ['', 'Power Convertor', 'VBAT1']
03-17 20:07:55 root 266:updating GUI with: 80
03-17 20:07:55 root 261:updating GUI message: 'Replicating zones'
03-17 20:07:55 replicate_layout.replicatelayout 708:Replicating zones
03-17 20:07:55 replicate_layout.replicatelayout 715:Replicating zones on sheet ['', '5V power share']
03-17 20:07:55 replicate_layout.replicatelayout 715:Replicating zones on sheet ['', 'Power Convertor', 'VBAT1']
03-17 20:07:55 root 261:updating GUI message: 'Replicating text'
03-17 20:07:55 replicate_layout.replicatelayout 773:Replicating text
03-17 20:07:55 replicate_layout.replicatelayout 780:Replicating text on sheet ['', '5V power share']
03-17 20:07:55 replicate_layout.replicatelayout 780:Replicating text on sheet ['', 'Power Convertor', 'VBAT1']
03-17 20:07:55 root 261:updating GUI message: 'Replicating drawings'
03-17 20:07:55 replicate_layout.replicatelayout 804:Replicating drawings
03-17 20:07:55 replicate_layout.replicatelayout 810:Replicating drawings on sheet ['', '5V power share']
03-17 20:07:55 replicate_layout.replicatelayout 810:Replicating drawings on sheet ['', 'Power Convertor', 'VBAT1']
03-17 20:07:55 replicate_layout.action_replicate_layout 201:Replication complete
+3
View File
@@ -0,0 +1,3 @@
(sym_lib_table
(lib (name "comm")(type "KiCad")(uri "${KIPRJMOD}/comm.kicad_sym")(options "")(descr ""))
)
-1
View File
@@ -4,4 +4,3 @@ Hierarchy_test/
Replicate_test/ Replicate_test/
replicate_layout.log replicate_layout.log
bom/ bom/
gerbers/
+22 -955
View File
File diff suppressed because it is too large Load Diff
+18 -138
View File
@@ -99,44 +99,6 @@
) )
) )
) )
(symbol "Device:R" (pin_numbers hide) (pin_names (offset 0)) (in_bom yes) (on_board yes)
(property "Reference" "R" (id 0) (at 2.032 0 90)
(effects (font (size 1.27 1.27)))
)
(property "Value" "R" (id 1) (at 0 0 90)
(effects (font (size 1.27 1.27)))
)
(property "Footprint" "" (id 2) (at -1.778 0 90)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "~" (id 3) (at 0 0 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "ki_keywords" "R res resistor" (id 4) (at 0 0 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "ki_description" "Resistor" (id 5) (at 0 0 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "ki_fp_filters" "R_*" (id 6) (at 0 0 0)
(effects (font (size 1.27 1.27)) hide)
)
(symbol "R_0_1"
(rectangle (start -1.016 -2.54) (end 1.016 2.54)
(stroke (width 0.254)) (fill (type none))
)
)
(symbol "R_1_1"
(pin passive line (at 0 3.81 270) (length 1.27)
(name "~" (effects (font (size 1.27 1.27))))
(number "1" (effects (font (size 1.27 1.27))))
)
(pin passive line (at 0 -3.81 90) (length 1.27)
(name "~" (effects (font (size 1.27 1.27))))
(number "2" (effects (font (size 1.27 1.27))))
)
)
)
(symbol "TCY_transistors:SiS413DN" (pin_names hide) (in_bom yes) (on_board yes) (symbol "TCY_transistors:SiS413DN" (pin_names hide) (in_bom yes) (on_board yes)
(property "Reference" "Q" (id 0) (at 8.89 2.54 0) (property "Reference" "Q" (id 0) (at 8.89 2.54 0)
(effects (font (size 1 1)) (justify left)) (effects (font (size 1 1)) (justify left))
@@ -276,12 +238,8 @@
) )
(junction (at 91.44 100.33) (diameter 0.9144) (color 0 0 0 0)) (junction (at 91.44 100.33) (diameter 0.9144) (color 0 0 0 0))
(junction (at 101.6 100.33) (diameter 0.9144) (color 0 0 0 0)) (junction (at 109.22 100.33) (diameter 1.016) (color 0 0 0 0))
(junction (at 120.65 100.33) (diameter 0.9144) (color 0 0 0 0)) (junction (at 146.05 100.33) (diameter 0.9144) (color 0 0 0 0))
(junction (at 129.54 87.63) (diameter 0.9144) (color 0 0 0 0))
(junction (at 138.43 100.33) (diameter 0.9144) (color 0 0 0 0))
(junction (at 154.94 100.33) (diameter 0.9144) (color 0 0 0 0))
(junction (at 163.83 87.63) (diameter 0.9144) (color 0 0 0 0))
(junction (at 177.9026 100.33) (diameter 0.9144) (color 0 0 0 0)) (junction (at 177.9026 100.33) (diameter 0.9144) (color 0 0 0 0))
(wire (pts (xy 85.09 100.33) (xy 91.44 100.33)) (wire (pts (xy 85.09 100.33) (xy 91.44 100.33))
@@ -316,7 +274,7 @@
(stroke (width 0) (type solid) (color 0 0 0 0)) (stroke (width 0) (type solid) (color 0 0 0 0))
(uuid 886a7fe0-592a-4344-9167-1b9474b4d521) (uuid 886a7fe0-592a-4344-9167-1b9474b4d521)
) )
(wire (pts (xy 91.44 100.33) (xy 101.6 100.33)) (wire (pts (xy 91.44 100.33) (xy 109.22 100.33))
(stroke (width 0) (type solid) (color 0 0 0 0)) (stroke (width 0) (type solid) (color 0 0 0 0))
(uuid 1780ecd2-3ddf-4c71-a66e-75241af3892b) (uuid 1780ecd2-3ddf-4c71-a66e-75241af3892b)
) )
@@ -324,63 +282,23 @@
(stroke (width 0) (type solid) (color 0 0 0 0)) (stroke (width 0) (type solid) (color 0 0 0 0))
(uuid 5a0b731d-3ff6-4d89-8fa2-ed7531d9e9f8) (uuid 5a0b731d-3ff6-4d89-8fa2-ed7531d9e9f8)
) )
(wire (pts (xy 101.6 100.33) (xy 120.65 100.33)) (wire (pts (xy 109.22 100.33) (xy 124.46 100.33))
(stroke (width 0) (type solid) (color 0 0 0 0)) (stroke (width 0) (type solid) (color 0 0 0 0))
(uuid 1780ecd2-3ddf-4c71-a66e-75241af3892b) (uuid 1780ecd2-3ddf-4c71-a66e-75241af3892b)
) )
(wire (pts (xy 120.65 87.63) (xy 129.54 87.63)) (wire (pts (xy 129.54 82.55) (xy 129.54 92.71))
(stroke (width 0) (type solid) (color 0 0 0 0))
(uuid e8d5ab89-e472-404c-94a4-83942d1c8ba1)
)
(wire (pts (xy 120.65 90.17) (xy 120.65 87.63))
(stroke (width 0) (type solid) (color 0 0 0 0))
(uuid e8d5ab89-e472-404c-94a4-83942d1c8ba1)
)
(wire (pts (xy 120.65 97.79) (xy 120.65 100.33))
(stroke (width 0) (type solid) (color 0 0 0 0))
(uuid 3b56f7f2-ba54-490d-8f81-2588b7538731)
)
(wire (pts (xy 120.65 100.33) (xy 124.46 100.33))
(stroke (width 0) (type solid) (color 0 0 0 0))
(uuid 1780ecd2-3ddf-4c71-a66e-75241af3892b)
)
(wire (pts (xy 129.54 82.55) (xy 129.54 87.63))
(stroke (width 0) (type solid) (color 0 0 0 0)) (stroke (width 0) (type solid) (color 0 0 0 0))
(uuid 025078fd-d2d3-4a24-87e9-2e929556f1be) (uuid 025078fd-d2d3-4a24-87e9-2e929556f1be)
) )
(wire (pts (xy 129.54 87.63) (xy 129.54 92.71)) (wire (pts (xy 134.62 100.33) (xy 146.05 100.33))
(stroke (width 0) (type solid) (color 0 0 0 0))
(uuid 025078fd-d2d3-4a24-87e9-2e929556f1be)
)
(wire (pts (xy 134.62 100.33) (xy 138.43 100.33))
(stroke (width 0) (type solid) (color 0 0 0 0)) (stroke (width 0) (type solid) (color 0 0 0 0))
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@@ -422,37 +340,37 @@
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@@ -476,44 +394,6 @@
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(property "Footprint" "TCY_passives:R_0603_1608Metric" (id 2) (at 118.872 93.98 90)
(effects (font (size 1.27 1.27)) hide)
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(uuid dc7d5727-2626-49ff-82cc-4264075bd7c5) (uuid dc7d5727-2626-49ff-82cc-4264075bd7c5)
+167 -173
View File
@@ -1293,7 +1293,7 @@
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@@ -1309,7 +1309,7 @@
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@@ -1327,7 +1327,7 @@
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@@ -1345,7 +1345,7 @@
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@@ -1363,7 +1363,7 @@
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@@ -1381,7 +1381,7 @@
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@@ -1399,7 +1399,7 @@
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@@ -1417,7 +1417,7 @@
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@@ -1435,7 +1435,7 @@
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@@ -1453,7 +1453,7 @@
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@@ -1471,7 +1471,7 @@
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@@ -1489,7 +1489,7 @@
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@@ -1507,7 +1507,7 @@
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@@ -1525,7 +1525,7 @@
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@@ -1543,7 +1543,7 @@
(symbol (lib_id "power:GND") (at 124.46 66.04 0) (symbol (lib_id "power:GND") (at 124.46 66.04 0)
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@@ -1561,7 +1561,7 @@
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@@ -1579,7 +1579,7 @@
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@@ -1597,7 +1597,7 @@
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(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Value" "GND" (id 1) (at 154.94 51.5526 0) (property "Value" "GND" (id 1) (at 154.94 51.5526 0)
@@ -1615,7 +1615,7 @@
(symbol (lib_id "power:GND") (at 167.64 66.04 0) (symbol (lib_id "power:GND") (at 167.64 66.04 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid df798d82-2f3c-4dfb-aea6-d6cc60b19134) (uuid df798d82-2f3c-4dfb-aea6-d6cc60b19134)
(property "Reference" "#PWR0321" (id 0) (at 167.64 72.39 0) (property "Reference" "#PWR0307" (id 0) (at 167.64 72.39 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Value" "GND" (id 1) (at 167.64 70.6026 0) (property "Value" "GND" (id 1) (at 167.64 70.6026 0)
@@ -1633,7 +1633,7 @@
(symbol (lib_id "power:GND") (at 176.53 46.99 0) (symbol (lib_id "power:GND") (at 176.53 46.99 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 49859834-77ba-4d2a-aedc-7002f2252039) (uuid 49859834-77ba-4d2a-aedc-7002f2252039)
(property "Reference" "#PWR0322" (id 0) (at 176.53 53.34 0) (property "Reference" "#PWR0308" (id 0) (at 176.53 53.34 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Value" "GND" (id 1) (at 176.53 51.5526 0) (property "Value" "GND" (id 1) (at 176.53 51.5526 0)
@@ -1651,7 +1651,7 @@
(symbol (lib_id "power:GND") (at 189.23 66.04 0) (symbol (lib_id "power:GND") (at 189.23 66.04 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid f971ccb3-793f-44b3-b583-09df7c4e15d4) (uuid f971ccb3-793f-44b3-b583-09df7c4e15d4)
(property "Reference" "#PWR0323" (id 0) (at 189.23 72.39 0) (property "Reference" "#PWR0309" (id 0) (at 189.23 72.39 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Value" "GND" (id 1) (at 189.23 70.6026 0) (property "Value" "GND" (id 1) (at 189.23 70.6026 0)
@@ -1669,7 +1669,7 @@
(symbol (lib_id "power:GND") (at 196.85 46.99 0) (symbol (lib_id "power:GND") (at 196.85 46.99 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 72eb244b-1077-4e62-96d6-68423f908d76) (uuid 72eb244b-1077-4e62-96d6-68423f908d76)
(property "Reference" "#PWR0324" (id 0) (at 196.85 53.34 0) (property "Reference" "#PWR0310" (id 0) (at 196.85 53.34 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Value" "GND" (id 1) (at 196.85 51.5526 0) (property "Value" "GND" (id 1) (at 196.85 51.5526 0)
@@ -1687,7 +1687,7 @@
(symbol (lib_id "power:GND") (at 254 148.59 0) (symbol (lib_id "power:GND") (at 254 148.59 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid b21a8832-1bc1-40ce-9097-33ecf26c90c9) (uuid b21a8832-1bc1-40ce-9097-33ecf26c90c9)
(property "Reference" "#PWR0325" (id 0) (at 254 154.94 0) (property "Reference" "#PWR0311" (id 0) (at 254 154.94 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Value" "GND" (id 1) (at 254 153.1526 0) (property "Value" "GND" (id 1) (at 254 153.1526 0)
@@ -1705,7 +1705,7 @@
(symbol (lib_id "Device:R") (at 45.72 52.07 0) (symbol (lib_id "Device:R") (at 45.72 52.07 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 046a5d50-76f9-451d-a070-7a08da1f4fe9) (uuid 046a5d50-76f9-451d-a070-7a08da1f4fe9)
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(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
) )
(property "Value" "1M" (id 1) (at 47.4981 53.9366 0) (property "Value" "1M" (id 1) (at 47.4981 53.9366 0)
@@ -1724,7 +1724,7 @@
(symbol (lib_id "Device:R") (at 45.72 87.63 0) (symbol (lib_id "Device:R") (at 45.72 87.63 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 70d55800-0bef-4cfa-ad2f-feae0810f250) (uuid 70d55800-0bef-4cfa-ad2f-feae0810f250)
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(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
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(property "Value" "1M" (id 1) (at 47.4981 89.4966 0) (property "Value" "1M" (id 1) (at 47.4981 89.4966 0)
@@ -1743,7 +1743,7 @@
(symbol (lib_id "Device:R") (at 45.72 113.03 0) (symbol (lib_id "Device:R") (at 45.72 113.03 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 60a83c79-7ad7-451f-83e1-42a524cbdd7c) (uuid 60a83c79-7ad7-451f-83e1-42a524cbdd7c)
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(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
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(property "Value" "1M" (id 1) (at 47.4981 114.8966 0) (property "Value" "1M" (id 1) (at 47.4981 114.8966 0)
@@ -1762,7 +1762,7 @@
(symbol (lib_id "Device:R") (at 45.72 138.43 0) (symbol (lib_id "Device:R") (at 45.72 138.43 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 9bd044e5-0267-4d7f-bf19-47397e17afe7) (uuid 9bd044e5-0267-4d7f-bf19-47397e17afe7)
(property "Reference" "R152" (id 0) (at 47.4981 137.5215 0) (property "Reference" "R142" (id 0) (at 47.4981 137.5215 0)
(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
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(property "Value" "1M" (id 1) (at 47.4981 140.2966 0) (property "Value" "1M" (id 1) (at 47.4981 140.2966 0)
@@ -1781,7 +1781,7 @@
(symbol (lib_id "Device:R") (at 45.72 163.83 0) (symbol (lib_id "Device:R") (at 45.72 163.83 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 397ff558-eb00-494b-8192-31162d254ac8) (uuid 397ff558-eb00-494b-8192-31162d254ac8)
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(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
) )
(property "Value" "1M" (id 1) (at 47.4981 165.6966 0) (property "Value" "1M" (id 1) (at 47.4981 165.6966 0)
@@ -1800,7 +1800,7 @@
(symbol (lib_id "Device:R") (at 55.88 58.42 90) (symbol (lib_id "Device:R") (at 55.88 58.42 90)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 5b8917f6-415c-4e19-9fb5-473471613ebf) (uuid 5b8917f6-415c-4e19-9fb5-473471613ebf)
(property "Reference" "R154" (id 0) (at 55.88 53.4374 90)) (property "Reference" "R144" (id 0) (at 55.88 53.4374 90))
(property "Value" "100K" (id 1) (at 55.88 56.2125 90)) (property "Value" "100K" (id 1) (at 55.88 56.2125 90))
(property "Footprint" "TCY_passives:R_0603_1608Metric" (id 2) (at 55.88 60.198 90) (property "Footprint" "TCY_passives:R_0603_1608Metric" (id 2) (at 55.88 60.198 90)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
@@ -1815,7 +1815,7 @@
(symbol (lib_id "Device:R") (at 55.88 93.98 90) (symbol (lib_id "Device:R") (at 55.88 93.98 90)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 128225de-697c-4a97-9a37-e758fde44eed) (uuid 128225de-697c-4a97-9a37-e758fde44eed)
(property "Reference" "R155" (id 0) (at 55.88 88.9974 90)) (property "Reference" "R145" (id 0) (at 55.88 88.9974 90))
(property "Value" "100K" (id 1) (at 55.88 91.7725 90)) (property "Value" "100K" (id 1) (at 55.88 91.7725 90))
(property "Footprint" "TCY_passives:R_0603_1608Metric" (id 2) (at 55.88 95.758 90) (property "Footprint" "TCY_passives:R_0603_1608Metric" (id 2) (at 55.88 95.758 90)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
@@ -1830,7 +1830,7 @@
(symbol (lib_id "Device:R") (at 55.88 119.38 90) (symbol (lib_id "Device:R") (at 55.88 119.38 90)
(in_bom yes) (on_board yes) (in_bom yes) (on_board yes)
(uuid 136eb723-df73-49f1-a527-adb94675c4aa) (uuid 136eb723-df73-49f1-a527-adb94675c4aa)
(property "Reference" "R156" (id 0) (at 55.88 114.3974 90)) (property "Reference" "R146" (id 0) (at 55.88 114.3974 90))
(property "Value" "100K" (id 1) (at 55.88 117.1725 90)) (property "Value" "100K" (id 1) (at 55.88 117.1725 90))
(property "Footprint" "TCY_passives:R_0603_1608Metric" (id 2) (at 55.88 121.158 90) (property "Footprint" "TCY_passives:R_0603_1608Metric" (id 2) (at 55.88 121.158 90)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
@@ -1845,7 +1845,7 @@
(symbol (lib_id "Device:R") (at 55.88 144.78 90) (symbol (lib_id "Device:R") (at 55.88 144.78 90)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 0b10c618-8767-4a3d-b85f-550342fdc849) (uuid 0b10c618-8767-4a3d-b85f-550342fdc849)
(property "Reference" "R157" (id 0) (at 55.88 139.7974 90)) (property "Reference" "R147" (id 0) (at 55.88 139.7974 90))
(property "Value" "100K" (id 1) (at 55.88 142.5725 90)) (property "Value" "100K" (id 1) (at 55.88 142.5725 90))
(property "Footprint" "TCY_passives:R_0603_1608Metric" (id 2) (at 55.88 146.558 90) (property "Footprint" "TCY_passives:R_0603_1608Metric" (id 2) (at 55.88 146.558 90)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
@@ -1860,7 +1860,7 @@
(symbol (lib_id "Device:R") (at 55.88 170.18 90) (symbol (lib_id "Device:R") (at 55.88 170.18 90)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 700014a3-802f-4c0f-9298-68466aff9e83) (uuid 700014a3-802f-4c0f-9298-68466aff9e83)
(property "Reference" "R158" (id 0) (at 55.88 165.1974 90)) (property "Reference" "R148" (id 0) (at 55.88 165.1974 90))
(property "Value" "100K" (id 1) (at 55.88 167.9725 90)) (property "Value" "100K" (id 1) (at 55.88 167.9725 90))
(property "Footprint" "TCY_passives:R_0603_1608Metric" (id 2) (at 55.88 171.958 90) (property "Footprint" "TCY_passives:R_0603_1608Metric" (id 2) (at 55.88 171.958 90)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
@@ -1875,7 +1875,7 @@
(symbol (lib_id "Device:C") (at 62.23 62.23 0) (symbol (lib_id "Device:C") (at 62.23 62.23 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 55dbff3e-6e0b-43db-b698-69e56ed17386) (uuid 55dbff3e-6e0b-43db-b698-69e56ed17386)
(property "Reference" "C138" (id 0) (at 65.1511 61.3215 0) (property "Reference" "C129" (id 0) (at 65.1511 61.3215 0)
(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
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(property "Value" "100nF" (id 1) (at 65.1511 64.0966 0) (property "Value" "100nF" (id 1) (at 65.1511 64.0966 0)
@@ -1894,7 +1894,7 @@
(symbol (lib_id "Device:C") (at 62.23 97.79 0) (symbol (lib_id "Device:C") (at 62.23 97.79 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid e8bb51ab-d939-4784-a489-def2547bdb3d) (uuid e8bb51ab-d939-4784-a489-def2547bdb3d)
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(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
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(property "Value" "100nF" (id 1) (at 65.1511 99.6566 0) (property "Value" "100nF" (id 1) (at 65.1511 99.6566 0)
@@ -1913,7 +1913,7 @@
(symbol (lib_id "Device:C") (at 62.23 123.19 0) (symbol (lib_id "Device:C") (at 62.23 123.19 0)
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(uuid 0d0a3ab6-e040-4eb0-8db0-2ce1e1d2138b) (uuid 0d0a3ab6-e040-4eb0-8db0-2ce1e1d2138b)
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(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
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(property "Value" "100nF" (id 1) (at 65.1511 125.0566 0) (property "Value" "100nF" (id 1) (at 65.1511 125.0566 0)
@@ -1932,7 +1932,7 @@
(symbol (lib_id "Device:C") (at 62.23 148.59 0) (symbol (lib_id "Device:C") (at 62.23 148.59 0)
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(uuid 4f116f87-7f00-46a2-8c25-26e7005e06eb) (uuid 4f116f87-7f00-46a2-8c25-26e7005e06eb)
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(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
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(property "Value" "100nF" (id 1) (at 65.1511 150.4566 0) (property "Value" "100nF" (id 1) (at 65.1511 150.4566 0)
@@ -1951,7 +1951,7 @@
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(uuid f444c82e-bfd4-43c4-ad99-599ee10a62d3) (uuid f444c82e-bfd4-43c4-ad99-599ee10a62d3)
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(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
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(property "Value" "100nF" (id 1) (at 65.1511 175.8566 0) (property "Value" "100nF" (id 1) (at 65.1511 175.8566 0)
@@ -1970,7 +1970,7 @@
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(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
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(property "Value" "100nF" (id 1) (at 133.7311 46.3166 0) (property "Value" "100nF" (id 1) (at 133.7311 46.3166 0)
@@ -1989,7 +1989,7 @@
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(uuid fe5a6196-1aee-4c44-9a1f-f65fcb6d0230) (uuid fe5a6196-1aee-4c44-9a1f-f65fcb6d0230)
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(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
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(property "Value" "100nF" (id 1) (at 155.3211 46.3166 0) (property "Value" "100nF" (id 1) (at 155.3211 46.3166 0)
@@ -2008,7 +2008,7 @@
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(in_bom yes) (on_board yes) (in_bom yes) (on_board yes)
(uuid cf6b7e71-1673-45ad-bd23-44be75ca0581) (uuid cf6b7e71-1673-45ad-bd23-44be75ca0581)
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(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
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(property "Value" "100nF" (id 1) (at 176.9111 46.3166 0) (property "Value" "100nF" (id 1) (at 176.9111 46.3166 0)
@@ -2027,7 +2027,7 @@
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(in_bom yes) (on_board yes) (in_bom yes) (on_board yes)
(uuid 3fac7229-4403-49cb-9986-819516ad2138) (uuid 3fac7229-4403-49cb-9986-819516ad2138)
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(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
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(property "Value" "100nF" (id 1) (at 197.2311 46.3166 0) (property "Value" "100nF" (id 1) (at 197.2311 46.3166 0)
@@ -2046,7 +2046,7 @@
(symbol (lib_id "74xx:74LV14") (at 78.74 58.42 0) (symbol (lib_id "74xx:74LV14") (at 78.74 58.42 0)
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(uuid 0b25e622-cea8-462d-a2cb-163ca209e2d5) (uuid 0b25e622-cea8-462d-a2cb-163ca209e2d5)
(property "Reference" "U51" (id 0) (at 78.74 50.6434 0)) (property "Reference" "U47" (id 0) (at 78.74 50.6434 0))
(property "Value" "74LV14" (id 1) (at 78.74 53.4185 0)) (property "Value" "74LV14" (id 1) (at 78.74 53.4185 0))
(property "Footprint" "Package_DFN_QFN:Texas_S-PVQFN-N14" (id 2) (at 78.74 58.42 0) (property "Footprint" "Package_DFN_QFN:Texas_S-PVQFN-N14" (id 2) (at 78.74 58.42 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
@@ -2061,7 +2061,7 @@
(symbol (lib_id "74xx:74LV14") (at 78.74 93.98 0) (symbol (lib_id "74xx:74LV14") (at 78.74 93.98 0)
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@@ -2332,39 +2358,7 @@
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+23 -31
View File
@@ -394,10 +394,10 @@
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(junction (at 184.15 101.6) (diameter 0.9144) (color 0 0 0 0)) (junction (at 184.15 101.6) (diameter 0.9144) (color 0 0 0 0))
@@ -1059,15 +1059,11 @@
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+3 -3
View File
@@ -684,7 +684,7 @@
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(uuid 8b2d9cbc-26e3-4621-b9e4-851a2738fb70) (uuid 8b2d9cbc-26e3-4621-b9e4-851a2738fb70)
(property "Reference" "#FLG023" (id 0) (at 168.91 76.835 0) (property "Reference" "#FLG020" (id 0) (at 168.91 76.835 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Value" "PWR_FLAG" (id 1) (at 168.91 75.1354 0)) (property "Value" "PWR_FLAG" (id 1) (at 168.91 75.1354 0))
@@ -716,7 +716,7 @@
(symbol (lib_id "power:PWR_FLAG") (at 168.91 113.03 0) (symbol (lib_id "power:PWR_FLAG") (at 168.91 113.03 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 4a4fc04e-d521-4c35-aa9f-6a2b72e92bab) (uuid 4a4fc04e-d521-4c35-aa9f-6a2b72e92bab)
(property "Reference" "#FLG024" (id 0) (at 168.91 111.125 0) (property "Reference" "#FLG021" (id 0) (at 168.91 111.125 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Value" "PWR_FLAG" (id 1) (at 168.91 109.4254 0)) (property "Value" "PWR_FLAG" (id 1) (at 168.91 109.4254 0))
+95917 -181409
View File
File diff suppressed because it is too large Load Diff
+4 -3
View File
@@ -1,10 +1,10 @@
{ {
"board": { "board": {
"active_layer": 31, "active_layer": 0,
"active_layer_preset": "", "active_layer_preset": "",
"auto_track_width": false, "auto_track_width": false,
"hidden_nets": [], "hidden_nets": [],
"high_contrast_mode": 0, "high_contrast_mode": 1,
"net_color_mode": 1, "net_color_mode": 1,
"opacity": { "opacity": {
"pads": 1.0, "pads": 1.0,
@@ -37,6 +37,7 @@
8, 8,
9, 9,
10, 10,
11,
12, 12,
13, 13,
14, 14,
@@ -63,7 +64,7 @@
36 36
], ],
"visible_layers": "7fcffff_80000007", "visible_layers": "7fcffff_80000007",
"zone_display_mode": 0 "zone_display_mode": 1
}, },
"meta": { "meta": {
"filename": "EPS.kicad_prl", "filename": "EPS.kicad_prl",
+6 -7
View File
@@ -33,9 +33,9 @@
"other_text_thickness": 0.15, "other_text_thickness": 0.15,
"other_text_upright": false, "other_text_upright": false,
"pads": { "pads": {
"drill": 0.0, "drill": 2.0,
"height": 0.43, "height": 4.0,
"width": 0.37 "width": 4.0
}, },
"silk_line_width": 0.15, "silk_line_width": 0.15,
"silk_text_italic": false, "silk_text_italic": false,
@@ -122,7 +122,6 @@
0.25, 0.25,
0.5, 0.5,
1.0, 1.0,
1.5,
2.0 2.0
], ],
"via_dimensions": [ "via_dimensions": [
@@ -358,9 +357,9 @@
{ {
"bus_width": 6.0, "bus_width": 6.0,
"clearance": 0.15, "clearance": 0.15,
"diff_pair_gap": 0.15, "diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25, "diff_pair_via_gap": 0.25,
"diff_pair_width": 0.15, "diff_pair_width": 0.2,
"line_style": 0, "line_style": 0,
"microvia_diameter": 0.5, "microvia_diameter": 0.5,
"microvia_drill": 0.2, "microvia_drill": 0.2,
@@ -423,7 +422,7 @@
"workbook_filename": "" "workbook_filename": ""
}, },
"page_layout_descr_file": "/home/petr/work/butcube/resources/kicad_page_layout.kicad_wks", "page_layout_descr_file": "/home/petr/work/butcube/resources/kicad_page_layout.kicad_wks",
"plot_directory": "/home/petr/", "plot_directory": "",
"spice_adjust_passive_values": false, "spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"", "spice_external_command": "spice \"%I\"",
"subpart_first_id": 65, "subpart_first_id": 65,
+12 -174
View File
@@ -1828,60 +1828,6 @@
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/855c8417-ab94-4328-91c9-4e7cdd76a6fe/3e102a28-d5a4-4d2c-b73e-7fe3de18252f/b21a8832-1bc1-40ce-9097-33ecf26c90c9" (path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/855c8417-ab94-4328-91c9-4e7cdd76a6fe/3e102a28-d5a4-4d2c-b73e-7fe3de18252f/b21a8832-1bc1-40ce-9097-33ecf26c90c9"
(reference "#PWR0325") (unit 1) (value "GND") (footprint "") (reference "#PWR0325") (unit 1) (value "GND") (footprint "")
) )
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/a1864510-e1e6-4848-b151-94afd18aebc0"
(reference "#PWR0326") (unit 1) (value "GND") (footprint "")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/2ee5a4ea-2cf5-4745-8c3f-c9acfbe1accc"
(reference "#PWR0327") (unit 1) (value "GND") (footprint "")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/8f885a33-2984-4462-b718-2da635648576"
(reference "#PWR0328") (unit 1) (value "GND") (footprint "")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/8952a37e-df2b-431f-b2c6-7cb2d0e2e80d"
(reference "#PWR0329") (unit 1) (value "GND") (footprint "")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/8e3acdd8-540d-4143-a322-05885b2d4f43"
(reference "#PWR0330") (unit 1) (value "GND") (footprint "")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/75d091be-771e-4bb7-a688-656f7f1e9114"
(reference "#PWR0331") (unit 1) (value "GND") (footprint "")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/6ed11e3c-e908-4a4e-877c-b916bd17990f"
(reference "#PWR0332") (unit 1) (value "GND") (footprint "")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/9e96f8c8-04ac-4f65-9f85-76f71750f16f"
(reference "#PWR0333") (unit 1) (value "GND") (footprint "")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/1a7a3456-0559-47da-8e0a-e8e08ac21cda"
(reference "#PWR0334") (unit 1) (value "GND") (footprint "")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/6fb8053f-42ce-42af-8e9e-aced75a63ce0/a1864510-e1e6-4848-b151-94afd18aebc0"
(reference "#PWR0335") (unit 1) (value "GND") (footprint "")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/6fb8053f-42ce-42af-8e9e-aced75a63ce0/2ee5a4ea-2cf5-4745-8c3f-c9acfbe1accc"
(reference "#PWR0336") (unit 1) (value "GND") (footprint "")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/6fb8053f-42ce-42af-8e9e-aced75a63ce0/8f885a33-2984-4462-b718-2da635648576"
(reference "#PWR0337") (unit 1) (value "GND") (footprint "")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/6fb8053f-42ce-42af-8e9e-aced75a63ce0/8952a37e-df2b-431f-b2c6-7cb2d0e2e80d"
(reference "#PWR0338") (unit 1) (value "GND") (footprint "")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/6fb8053f-42ce-42af-8e9e-aced75a63ce0/8e3acdd8-540d-4143-a322-05885b2d4f43"
(reference "#PWR0339") (unit 1) (value "GND") (footprint "")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/6fb8053f-42ce-42af-8e9e-aced75a63ce0/75d091be-771e-4bb7-a688-656f7f1e9114"
(reference "#PWR0340") (unit 1) (value "GND") (footprint "")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/6fb8053f-42ce-42af-8e9e-aced75a63ce0/6ed11e3c-e908-4a4e-877c-b916bd17990f"
(reference "#PWR0341") (unit 1) (value "GND") (footprint "")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/6fb8053f-42ce-42af-8e9e-aced75a63ce0/9e96f8c8-04ac-4f65-9f85-76f71750f16f"
(reference "#PWR0342") (unit 1) (value "GND") (footprint "")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/6fb8053f-42ce-42af-8e9e-aced75a63ce0/1a7a3456-0559-47da-8e0a-e8e08ac21cda"
(reference "#PWR0343") (unit 1) (value "GND") (footprint "")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/8b26e5ec-531f-4d14-9545-53740a389728" (path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/8b26e5ec-531f-4d14-9545-53740a389728"
(reference "C1") (unit 1) (value "1uF") (footprint "TCY_passives:C_0603_1608Metric") (reference "C1") (unit 1) (value "1uF") (footprint "TCY_passives:C_0603_1608Metric")
) )
@@ -2320,24 +2266,6 @@
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/855c8417-ab94-4328-91c9-4e7cdd76a6fe/3e102a28-d5a4-4d2c-b73e-7fe3de18252f/3fac7229-4403-49cb-9986-819516ad2138" (path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/855c8417-ab94-4328-91c9-4e7cdd76a6fe/3e102a28-d5a4-4d2c-b73e-7fe3de18252f/3fac7229-4403-49cb-9986-819516ad2138"
(reference "C146") (unit 1) (value "100nF") (footprint "TCY_passives:C_0603_1608Metric") (reference "C146") (unit 1) (value "100nF") (footprint "TCY_passives:C_0603_1608Metric")
) )
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/7deaa9e8-74f5-4955-aa50-be0b27bd3e2d"
(reference "C147") (unit 1) (value "100nF") (footprint "TCY_passives:C_0603_1608Metric")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/9e954769-7e29-4b7a-a02c-3d74bec395be"
(reference "C148") (unit 1) (value "100nF") (footprint "TCY_passives:C_0603_1608Metric")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/63246316-2ce3-4032-a218-4966a4c41296"
(reference "C149") (unit 1) (value "100nF") (footprint "TCY_passives:C_0603_1608Metric")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/6fb8053f-42ce-42af-8e9e-aced75a63ce0/7deaa9e8-74f5-4955-aa50-be0b27bd3e2d"
(reference "C150") (unit 1) (value "100nF") (footprint "TCY_passives:C_0603_1608Metric")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/6fb8053f-42ce-42af-8e9e-aced75a63ce0/9e954769-7e29-4b7a-a02c-3d74bec395be"
(reference "C151") (unit 1) (value "100nF") (footprint "TCY_passives:C_0603_1608Metric")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/6fb8053f-42ce-42af-8e9e-aced75a63ce0/63246316-2ce3-4032-a218-4966a4c41296"
(reference "C152") (unit 1) (value "100nF") (footprint "TCY_passives:C_0603_1608Metric")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/69a229f7-d3f6-4b7d-9358-aa1002ac32e6/8e26cb3e-a2da-4523-b59f-85315bbbed25" (path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/69a229f7-d3f6-4b7d-9358-aa1002ac32e6/8e26cb3e-a2da-4523-b59f-85315bbbed25"
(reference "D1") (unit 1) (value "YELLOW") (footprint "LED_SMD:LED_0603_1608Metric_Castellated") (reference "D1") (unit 1) (value "YELLOW") (footprint "LED_SMD:LED_0603_1608Metric_Castellated")
) )
@@ -2398,24 +2326,6 @@
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/e90aa45b-e371-4d9f-a40f-45b62d6b0cc2/4813e8c7-3f5a-4c5f-98f0-ec2a381e611e/9135e2df-d381-43ba-ab0c-de88b9a6488d" (path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/e90aa45b-e371-4d9f-a40f-45b62d6b0cc2/4813e8c7-3f5a-4c5f-98f0-ec2a381e611e/9135e2df-d381-43ba-ab0c-de88b9a6488d"
(reference "D20") (unit 1) (value "3V3") (footprint "Diode_SMD:D_SOD-323F") (reference "D20") (unit 1) (value "3V3") (footprint "Diode_SMD:D_SOD-323F")
) )
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/a8b33b11-d138-49cb-a644-bab7c142508e"
(reference "D21") (unit 1) (value "3V3") (footprint "TCY_passives:D_0603_1608Metric")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/44ae4c76-d19c-428a-a4dd-1789aec37a1b"
(reference "D22") (unit 1) (value "3V3") (footprint "TCY_passives:D_0603_1608Metric")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/7e00f11d-5808-4d75-883e-1b1e75d75a2e"
(reference "D23") (unit 1) (value "3V3") (footprint "TCY_passives:D_0603_1608Metric")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/6fb8053f-42ce-42af-8e9e-aced75a63ce0/a8b33b11-d138-49cb-a644-bab7c142508e"
(reference "D24") (unit 1) (value "3V3") (footprint "TCY_passives:D_0603_1608Metric")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/6fb8053f-42ce-42af-8e9e-aced75a63ce0/44ae4c76-d19c-428a-a4dd-1789aec37a1b"
(reference "D25") (unit 1) (value "3V3") (footprint "TCY_passives:D_0603_1608Metric")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/6fb8053f-42ce-42af-8e9e-aced75a63ce0/7e00f11d-5808-4d75-883e-1b1e75d75a2e"
(reference "D26") (unit 1) (value "3V3") (footprint "TCY_passives:D_0603_1608Metric")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/69a229f7-d3f6-4b7d-9358-aa1002ac32e6/79ded3a0-7353-4e96-a9b4-096f2f4cc987" (path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/69a229f7-d3f6-4b7d-9358-aa1002ac32e6/79ded3a0-7353-4e96-a9b4-096f2f4cc987"
(reference "F1") (unit 1) (value "10A") (footprint "Fuse:Fuse_1206_3216Metric") (reference "F1") (unit 1) (value "10A") (footprint "Fuse:Fuse_1206_3216Metric")
) )
@@ -2470,6 +2380,18 @@
(path "/bf4313bb-3c20-48f9-91dc-f33dc0ea2294" (path "/bf4313bb-3c20-48f9-91dc-f33dc0ea2294"
(reference "H4") (unit 1) (value "M3") (footprint "MountingHole:MountingHole_3.2mm_M3_Pad_Via") (reference "H4") (unit 1) (value "M3") (footprint "MountingHole:MountingHole_3.2mm_M3_Pad_Via")
) )
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/a54ccecb-328a-43f8-87f7-f271eb3ab8a9"
(reference "H5") (unit 1) (value "MountingHole") (footprint "MountingHole:MountingHole_3.2mm_M3_Pad_Via")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/a54ccecb-328a-43f8-87f7-f271eb3ab8a9"
(reference "H6") (unit 1) (value "MountingHole") (footprint "MountingHole:MountingHole_3.2mm_M3_Pad_Via")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/e90aa45b-e371-4d9f-a40f-45b62d6b0cc2/bcb184fa-cb43-4f8a-880d-f0338c82df5f"
(reference "H7") (unit 1) (value "MountingHole") (footprint "MountingHole:MountingHole_3.2mm_M3_Pad_Via")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/e90aa45b-e371-4d9f-a40f-45b62d6b0cc2/bcb184fa-cb43-4f8a-880d-f0338c82df5f"
(reference "H8") (unit 1) (value "MountingHole") (footprint "MountingHole:MountingHole_3.2mm_M3_Pad_Via")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/d0e7f43c-19e1-457f-9b3c-08ae18c73b14/4c6d1bf1-6b05-46e1-bcde-fe7eaff4737b" (path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/d0e7f43c-19e1-457f-9b3c-08ae18c73b14/4c6d1bf1-6b05-46e1-bcde-fe7eaff4737b"
(reference "J1") (unit 1) (value "Solar_X1") (footprint "TCY_connectors:Amphenol_10114830-11102LF_1x02_P1.25mm_Horizontal") (reference "J1") (unit 1) (value "Solar_X1") (footprint "TCY_connectors:Amphenol_10114830-11102LF_1x02_P1.25mm_Horizontal")
) )
@@ -2710,24 +2632,6 @@
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/e90aa45b-e371-4d9f-a40f-45b62d6b0cc2/4813e8c7-3f5a-4c5f-98f0-ec2a381e611e/4f984924-e775-4f93-861a-4954ba37a68e" (path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/e90aa45b-e371-4d9f-a40f-45b62d6b0cc2/4813e8c7-3f5a-4c5f-98f0-ec2a381e611e/4f984924-e775-4f93-861a-4954ba37a68e"
(reference "Q28") (unit 1) (value "SiS413DN") (footprint "Package_SO:Vishay_PowerPAK_1212-8_Single") (reference "Q28") (unit 1) (value "SiS413DN") (footprint "Package_SO:Vishay_PowerPAK_1212-8_Single")
) )
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/aa236148-d1ab-4ad6-a4bd-c30b5e8c91ad"
(reference "Q29") (unit 1) (value "DMP21D6UFD") (footprint "TCY_IC:DFN-3_1.2x1.2mm")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/fc54234d-47cb-432d-b5e3-86586d9f6d22"
(reference "Q30") (unit 1) (value "DMP21D6UFD") (footprint "TCY_IC:DFN-3_1.2x1.2mm")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/ee83b59d-62c4-4cf3-a784-dbe0ed1ae579"
(reference "Q31") (unit 1) (value "DMP21D6UFD") (footprint "TCY_IC:DFN-3_1.2x1.2mm")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/6fb8053f-42ce-42af-8e9e-aced75a63ce0/aa236148-d1ab-4ad6-a4bd-c30b5e8c91ad"
(reference "Q32") (unit 1) (value "DMP21D6UFD") (footprint "TCY_IC:DFN-3_1.2x1.2mm")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/6fb8053f-42ce-42af-8e9e-aced75a63ce0/fc54234d-47cb-432d-b5e3-86586d9f6d22"
(reference "Q33") (unit 1) (value "DMP21D6UFD") (footprint "TCY_IC:DFN-3_1.2x1.2mm")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/6fb8053f-42ce-42af-8e9e-aced75a63ce0/ee83b59d-62c4-4cf3-a784-dbe0ed1ae579"
(reference "Q34") (unit 1) (value "DMP21D6UFD") (footprint "TCY_IC:DFN-3_1.2x1.2mm")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/69a229f7-d3f6-4b7d-9358-aa1002ac32e6/e94a69a1-0efb-4192-86ff-8fae8a732a82" (path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/69a229f7-d3f6-4b7d-9358-aa1002ac32e6/e94a69a1-0efb-4192-86ff-8fae8a732a82"
(reference "R1") (unit 1) (value "10k") (footprint "TCY_passives:R_0603_1608Metric") (reference "R1") (unit 1) (value "10k") (footprint "TCY_passives:R_0603_1608Metric")
) )
@@ -3202,54 +3106,6 @@
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/855c8417-ab94-4328-91c9-4e7cdd76a6fe/3e102a28-d5a4-4d2c-b73e-7fe3de18252f/700014a3-802f-4c0f-9298-68466aff9e83" (path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/855c8417-ab94-4328-91c9-4e7cdd76a6fe/3e102a28-d5a4-4d2c-b73e-7fe3de18252f/700014a3-802f-4c0f-9298-68466aff9e83"
(reference "R158") (unit 1) (value "100K") (footprint "TCY_passives:R_0603_1608Metric") (reference "R158") (unit 1) (value "100K") (footprint "TCY_passives:R_0603_1608Metric")
) )
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/2e27e58e-8f90-42a1-9d4c-f7117a6341d3"
(reference "R159") (unit 1) (value "270k") (footprint "TCY_passives:R_0603_1608Metric")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/b0e2e296-e8aa-4e01-bd19-ea78e95b2c40"
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(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/142af4fb-258f-42b4-9b99-cdac598a902d"
(reference "R161") (unit 1) (value "270k") (footprint "TCY_passives:R_0603_1608Metric")
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(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/f1845307-a6bb-401e-b79c-0498bf7eba45"
(reference "R162") (unit 1) (value "270k") (footprint "TCY_passives:R_0603_1608Metric")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/7195a86d-d0c2-4213-8132-1b9cdbb27200"
(reference "R163") (unit 1) (value "270k") (footprint "TCY_passives:R_0603_1608Metric")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/196a980d-9b64-4766-9189-f332b9984b47"
(reference "R164") (unit 1) (value "270k") (footprint "TCY_passives:R_0603_1608Metric")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/855c8417-ab94-4328-91c9-4e7cdd76a6fe/f5ae3793-4c1d-445b-b18c-d145e97e5904"
(reference "R165") (unit 1) (value "1M") (footprint "TCY_passives:R_0603_1608Metric")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/855c8417-ab94-4328-91c9-4e7cdd76a6fe/b1ccc018-1f91-4655-b7fd-554933fe59e3"
(reference "R166") (unit 1) (value "1M") (footprint "TCY_passives:R_0603_1608Metric")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/6fb8053f-42ce-42af-8e9e-aced75a63ce0/2e27e58e-8f90-42a1-9d4c-f7117a6341d3"
(reference "R167") (unit 1) (value "270k") (footprint "TCY_passives:R_0603_1608Metric")
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(reference "R168") (unit 1) (value "270k") (footprint "TCY_passives:R_0603_1608Metric")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/6fb8053f-42ce-42af-8e9e-aced75a63ce0/142af4fb-258f-42b4-9b99-cdac598a902d"
(reference "R169") (unit 1) (value "270k") (footprint "TCY_passives:R_0603_1608Metric")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/6fb8053f-42ce-42af-8e9e-aced75a63ce0/f1845307-a6bb-401e-b79c-0498bf7eba45"
(reference "R170") (unit 1) (value "270k") (footprint "TCY_passives:R_0603_1608Metric")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/6fb8053f-42ce-42af-8e9e-aced75a63ce0/7195a86d-d0c2-4213-8132-1b9cdbb27200"
(reference "R171") (unit 1) (value "270k") (footprint "TCY_passives:R_0603_1608Metric")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/6fb8053f-42ce-42af-8e9e-aced75a63ce0/196a980d-9b64-4766-9189-f332b9984b47"
(reference "R172") (unit 1) (value "270k") (footprint "TCY_passives:R_0603_1608Metric")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/855c8417-ab94-4328-91c9-4e7cdd76a6fe/f5ae3793-4c1d-445b-b18c-d145e97e5904"
(reference "R173") (unit 1) (value "1M") (footprint "TCY_passives:R_0603_1608Metric")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/855c8417-ab94-4328-91c9-4e7cdd76a6fe/b1ccc018-1f91-4655-b7fd-554933fe59e3"
(reference "R174") (unit 1) (value "1M") (footprint "TCY_passives:R_0603_1608Metric")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/e90aa45b-e371-4d9f-a40f-45b62d6b0cc2/a12e4ae2-0082-44ab-871d-8bf2750427af/a44da014-6bbf-4eff-aa85-6f77eb7124cc" (path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/e90aa45b-e371-4d9f-a40f-45b62d6b0cc2/a12e4ae2-0082-44ab-871d-8bf2750427af/a44da014-6bbf-4eff-aa85-6f77eb7124cc"
(reference "RV1") (unit 1) (value "100k") (footprint "TCY_passives:RV_3x3.6") (reference "RV1") (unit 1) (value "100k") (footprint "TCY_passives:RV_3x3.6")
) )
@@ -3502,24 +3358,6 @@
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/855c8417-ab94-4328-91c9-4e7cdd76a6fe/3e102a28-d5a4-4d2c-b73e-7fe3de18252f/972f5450-4560-4f4f-83c1-8ac5b5730b98" (path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/855c8417-ab94-4328-91c9-4e7cdd76a6fe/3e102a28-d5a4-4d2c-b73e-7fe3de18252f/972f5450-4560-4f4f-83c1-8ac5b5730b98"
(reference "TP76") (unit 1) (value "SEP_LOG_EN") (footprint "TCY_connectors:TestPoint_Pad_D0.5mm") (reference "TP76") (unit 1) (value "SEP_LOG_EN") (footprint "TCY_connectors:TestPoint_Pad_D0.5mm")
) )
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/d8963118-29a9-4b04-b202-d877eb5066b2"
(reference "TP77") (unit 1) (value "ADC_VBAT_DIV") (footprint "TCY_connectors:TestPoint_Pad_D0.5mm")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/61aeab40-3d22-446a-a98d-3a359661da8f"
(reference "TP78") (unit 1) (value "ADC_3V3_DIV") (footprint "TCY_connectors:TestPoint_Pad_D0.5mm")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/d8896a17-b75b-42f3-9780-43492aac4e87"
(reference "TP79") (unit 1) (value "ADC_5V_DIV") (footprint "TCY_connectors:TestPoint_Pad_D0.5mm")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/6fb8053f-42ce-42af-8e9e-aced75a63ce0/d8963118-29a9-4b04-b202-d877eb5066b2"
(reference "TP80") (unit 1) (value "ADC_VBAT_DIV") (footprint "TCY_connectors:TestPoint_Pad_D0.5mm")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/6fb8053f-42ce-42af-8e9e-aced75a63ce0/61aeab40-3d22-446a-a98d-3a359661da8f"
(reference "TP81") (unit 1) (value "ADC_3V3_DIV") (footprint "TCY_connectors:TestPoint_Pad_D0.5mm")
)
(path "/4b3a0e0d-cdd4-41ca-aa78-0f9d521766f0/6fb8053f-42ce-42af-8e9e-aced75a63ce0/d8896a17-b75b-42f3-9780-43492aac4e87"
(reference "TP82") (unit 1) (value "ADC_5V_DIV") (footprint "TCY_connectors:TestPoint_Pad_D0.5mm")
)
(path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/184f183c-0212-4679-90e6-e664e8ed9ae3" (path "/3fbfe5f5-450c-4c51-813c-f3d5ddddd4e3/6fb8053f-42ce-42af-8e9e-aced75a63ce0/184f183c-0212-4679-90e6-e664e8ed9ae3"
(reference "U1") (unit 1) (value "ADS7038") (footprint "Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm") (reference "U1") (unit 1) (value "ADS7038") (footprint "Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm")
) )
+58 -27
View File
@@ -13,6 +13,32 @@
) )
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(symbol "Mechanical:MountingHole" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
(property "Reference" "H" (id 0) (at 0 5.08 0)
(effects (font (size 1.27 1.27)))
)
(property "Value" "MountingHole" (id 1) (at 0 3.175 0)
(effects (font (size 1.27 1.27)))
)
(property "Footprint" "" (id 2) (at 0 0 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "~" (id 3) (at 0 0 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "ki_keywords" "mounting hole" (id 4) (at 0 0 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "ki_description" "Mounting Hole without connection" (id 5) (at 0 0 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "ki_fp_filters" "MountingHole*" (id 6) (at 0 0 0)
(effects (font (size 1.27 1.27)) hide)
)
(symbol "MountingHole_0_1"
(circle (center 0 0) (radius 1.27) (stroke (width 1.27)) (fill (type none)))
)
)
) )
(junction (at 247.65 50.8) (diameter 0.9144) (color 0 0 0 0)) (junction (at 247.65 50.8) (diameter 0.9144) (color 0 0 0 0))
@@ -148,29 +174,25 @@
(stroke (width 0) (type solid) (color 0 0 0 0)) (stroke (width 0) (type solid) (color 0 0 0 0))
(uuid 3e281d36-5ce1-4179-bd40-3bc37cf8938f) (uuid 3e281d36-5ce1-4179-bd40-3bc37cf8938f)
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(stroke (width 0) (type solid) (color 0 0 0 0)) (stroke (width 0) (type solid) (color 0 0 0 0))
(uuid 7c962bcc-b749-47bd-822e-2b28583867f0) (uuid 7c962bcc-b749-47bd-822e-2b28583867f0)
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(uuid 67646b95-49b2-4b7a-b030-32ed09a5c982) (uuid 67646b95-49b2-4b7a-b030-32ed09a5c982)
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(stroke (width 0) (type solid) (color 0 0 0 0)) (stroke (width 0) (type solid) (color 0 0 0 0))
@@ -343,6 +365,23 @@
(uuid bd11cae9-7b1b-4194-bd63-088eb328bd0b) (uuid bd11cae9-7b1b-4194-bd63-088eb328bd0b)
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(symbol (lib_id "Mechanical:MountingHole") (at 157.48 191.77 0)
(in_bom yes) (on_board yes) (fields_autoplaced)
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(effects (font (size 1.27 1.27)) (justify left))
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(property "Value" "MountingHole" (id 1) (at 160.0201 193.6366 0)
(effects (font (size 1.27 1.27)) (justify left))
)
(property "Footprint" "MountingHole:MountingHole_3.2mm_M3_Pad_Via" (id 2) (at 157.48 191.77 0)
(effects (font (size 1.27 1.27)) hide)
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(property "Datasheet" "~" (id 3) (at 157.48 191.77 0)
(effects (font (size 1.27 1.27)) hide)
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(fill (color 72 72 72 1.0000)) (fill (color 72 72 72 1.0000))
@@ -385,30 +424,26 @@
(effects (font (size 1.27 1.27)) (justify right)) (effects (font (size 1.27 1.27)) (justify right))
(uuid 9ed64657-e5f1-432f-a56c-f56cd7365a38) (uuid 9ed64657-e5f1-432f-a56c-f56cd7365a38)
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(pin "~{CS}" input (at 218.44 140.97 180) (pin "~{CS}" input (at 218.44 144.78 180)
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(pin "MISO" input (at 218.44 129.54 180) (pin "MISO" input (at 218.44 133.35 180)
(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
(uuid 7a502a62-53b4-47cc-a07f-d99681cf6f12) (uuid 7a502a62-53b4-47cc-a07f-d99681cf6f12)
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(pin "MOSI" input (at 218.44 133.35 180) (pin "MOSI" input (at 218.44 137.16 180)
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(pin "CLK" input (at 218.44 137.16 180) (pin "CLK" input (at 218.44 140.97 180)
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(pin "POWER" input (at 218.44 125.73 180) (pin "POWER" input (at 218.44 128.27 180)
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(effects (font (size 1.27 1.27)) (justify left))
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(sheet (at 109.22 45.72) (size 25.4 17.78) (sheet (at 109.22 45.72) (size 25.4 17.78)
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(pin "ADC_CS" input (at 193.04 140.97 0) (pin "ADC_CS" input (at 193.04 144.78 0)
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(pin "SPI_SCK" input (at 193.04 137.16 0) (pin "SPI_SCK" input (at 193.04 140.97 0)
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(uuid 30c674ee-e46b-4f7d-a717-e203df9bb8ba) (uuid 30c674ee-e46b-4f7d-a717-e203df9bb8ba)
) )
(pin "SPI_MISO" input (at 193.04 129.54 0) (pin "SPI_MISO" input (at 193.04 133.35 0)
(effects (font (size 1.27 1.27)) (justify right)) (effects (font (size 1.27 1.27)) (justify right))
(uuid c58a7519-2d64-4265-a558-80e9e9728464) (uuid c58a7519-2d64-4265-a558-80e9e9728464)
) )
(pin "SPI_MOSI" input (at 193.04 133.35 0) (pin "SPI_MOSI" input (at 193.04 137.16 0)
(effects (font (size 1.27 1.27)) (justify right)) (effects (font (size 1.27 1.27)) (justify right))
(uuid 95fe481f-c7dc-4741-b116-e117eafdde43) (uuid 95fe481f-c7dc-4741-b116-e117eafdde43)
) )
@@ -629,10 +664,6 @@
(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
(uuid c2b61890-eec5-4774-8645-4351768df160) (uuid c2b61890-eec5-4774-8645-4351768df160)
) )
(pin "ADC_CONV_EN" input (at 193.04 144.78 0)
(effects (font (size 1.27 1.27)) (justify right))
(uuid 64bd5426-66ca-40db-a5db-6eeca1cc65f8)
)
) )
(sheet (at 151.13 48.26) (size 24.13 16.51) (sheet (at 151.13 48.26) (size 24.13 16.51)
+1 -8
View File
@@ -1429,6 +1429,7 @@
(no_connect (at 34.29 44.45) (uuid e10ebe7a-9370-45d7-a3c2-ff70ed0cc961)) (no_connect (at 34.29 44.45) (uuid e10ebe7a-9370-45d7-a3c2-ff70ed0cc961))
(no_connect (at 97.79 43.18) (uuid f7fb9913-3a3a-4daa-b482-30297d986cca)) (no_connect (at 97.79 43.18) (uuid f7fb9913-3a3a-4daa-b482-30297d986cca))
(no_connect (at 113.03 92.71) (uuid 1232c659-44b8-4817-a1fe-4b39c860e5ba))
(no_connect (at 113.03 105.41) (uuid 1232c659-44b8-4817-a1fe-4b39c860e5ba)) (no_connect (at 113.03 105.41) (uuid 1232c659-44b8-4817-a1fe-4b39c860e5ba))
(no_connect (at 143.51 110.49) (uuid 1232c659-44b8-4817-a1fe-4b39c860e5ba)) (no_connect (at 143.51 110.49) (uuid 1232c659-44b8-4817-a1fe-4b39c860e5ba))
(no_connect (at 148.59 31.75) (uuid b20a8eeb-8658-40fb-9401-7e2b7ffe47d2)) (no_connect (at 148.59 31.75) (uuid b20a8eeb-8658-40fb-9401-7e2b7ffe47d2))
@@ -1573,10 +1574,6 @@
(stroke (width 0) (type solid) (color 0 0 0 0)) (stroke (width 0) (type solid) (color 0 0 0 0))
(uuid be3bcb00-1ab3-4253-805b-5c8bc155ddd4) (uuid be3bcb00-1ab3-4253-805b-5c8bc155ddd4)
) )
(wire (pts (xy 102.87 92.71) (xy 113.03 92.71))
(stroke (width 0) (type solid) (color 0 0 0 0))
(uuid a68db038-0e60-42a6-b34f-37625f95f273)
)
(wire (pts (xy 102.87 95.25) (xy 113.03 95.25)) (wire (pts (xy 102.87 95.25) (xy 113.03 95.25))
(stroke (width 0) (type solid) (color 0 0 0 0)) (stroke (width 0) (type solid) (color 0 0 0 0))
(uuid afb276a0-9593-4e59-b858-16d8334750ba) (uuid afb276a0-9593-4e59-b858-16d8334750ba)
@@ -2697,10 +2694,6 @@
(effects (font (size 1.27 1.27)) (justify right)) (effects (font (size 1.27 1.27)) (justify right))
(uuid 31ea30a3-15bb-4267-a23f-9c39d956505f) (uuid 31ea30a3-15bb-4267-a23f-9c39d956505f)
) )
(hierarchical_label "ADC_CONV_EN" (shape input) (at 102.87 92.71 180)
(effects (font (size 1.27 1.27)) (justify right))
(uuid ed30faac-7802-4358-acbf-1181939f0d83)
)
(hierarchical_label "1V8_EN" (shape input) (at 102.87 110.49 180) (hierarchical_label "1V8_EN" (shape input) (at 102.87 110.49 180)
(effects (font (size 1.27 1.27)) (justify right)) (effects (font (size 1.27 1.27)) (justify right))
(uuid 3a18d311-bf07-4917-bc3e-c746a98fcb26) (uuid 3a18d311-bf07-4917-bc3e-c746a98fcb26)
+39 -39
View File
@@ -1354,7 +1354,7 @@
(symbol (lib_id "power:PWR_FLAG") (at 106.68 83.82 0) (symbol (lib_id "power:PWR_FLAG") (at 106.68 83.82 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 672f3a48-7f1a-49e2-9ecd-0c94f5637313) (uuid 672f3a48-7f1a-49e2-9ecd-0c94f5637313)
(property "Reference" "#FLG012" (id 0) (at 106.68 81.915 0) (property "Reference" "#FLG03" (id 0) (at 106.68 81.915 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Value" "PWR_FLAG" (id 1) (at 106.68 80.2154 0)) (property "Value" "PWR_FLAG" (id 1) (at 106.68 80.2154 0))
@@ -1370,7 +1370,7 @@
(symbol (lib_id "power:PWR_FLAG") (at 153.67 83.82 0) (symbol (lib_id "power:PWR_FLAG") (at 153.67 83.82 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 348d4dc6-647c-4ca1-a2c3-aae604cf9f2d) (uuid 348d4dc6-647c-4ca1-a2c3-aae604cf9f2d)
(property "Reference" "#FLG013" (id 0) (at 153.67 81.915 0) (property "Reference" "#FLG04" (id 0) (at 153.67 81.915 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Value" "PWR_FLAG" (id 1) (at 153.67 80.2154 0)) (property "Value" "PWR_FLAG" (id 1) (at 153.67 80.2154 0))
@@ -1386,7 +1386,7 @@
(symbol (lib_id "power:PWR_FLAG") (at 193.04 83.82 0) (symbol (lib_id "power:PWR_FLAG") (at 193.04 83.82 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 9504bd17-e2f2-4cf7-94d5-be1ef5a4299b) (uuid 9504bd17-e2f2-4cf7-94d5-be1ef5a4299b)
(property "Reference" "#FLG014" (id 0) (at 193.04 81.915 0) (property "Reference" "#FLG05" (id 0) (at 193.04 81.915 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Value" "PWR_FLAG" (id 1) (at 193.04 80.2154 0)) (property "Value" "PWR_FLAG" (id 1) (at 193.04 80.2154 0))
@@ -1402,7 +1402,7 @@
(symbol (lib_id "power:PWR_FLAG") (at 234.95 83.82 0) (symbol (lib_id "power:PWR_FLAG") (at 234.95 83.82 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid daf0328f-0a91-4487-bc78-2148725b11af) (uuid daf0328f-0a91-4487-bc78-2148725b11af)
(property "Reference" "#FLG015" (id 0) (at 234.95 81.915 0) (property "Reference" "#FLG06" (id 0) (at 234.95 81.915 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Value" "PWR_FLAG" (id 1) (at 234.95 80.2154 0)) (property "Value" "PWR_FLAG" (id 1) (at 234.95 80.2154 0))
@@ -1418,7 +1418,7 @@
(symbol (lib_id "Connector:TestPoint") (at 201.93 46.99 0) (symbol (lib_id "Connector:TestPoint") (at 201.93 46.99 0)
(in_bom yes) (on_board yes) (in_bom yes) (on_board yes)
(uuid 043a26d0-03b4-491b-88a5-d1d7df9705b1) (uuid 043a26d0-03b4-491b-88a5-d1d7df9705b1)
(property "Reference" "TP26" (id 0) (at 203.3271 40.43 0) (property "Reference" "TP9" (id 0) (at 203.3271 40.43 0)
(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
) )
(property "Value" "SYS_I" (id 1) (at 203.3271 43.2051 0) (property "Value" "SYS_I" (id 1) (at 203.3271 43.2051 0)
@@ -1436,7 +1436,7 @@
(symbol (lib_id "Connector:TestPoint") (at 243.84 83.82 0) (symbol (lib_id "Connector:TestPoint") (at 243.84 83.82 0)
(in_bom yes) (on_board yes) (in_bom yes) (on_board yes)
(uuid 14cc1790-c870-47a9-9a24-ed92d3a0ea56) (uuid 14cc1790-c870-47a9-9a24-ed92d3a0ea56)
(property "Reference" "TP27" (id 0) (at 245.2371 77.26 0) (property "Reference" "TP10" (id 0) (at 245.2371 77.26 0)
(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
) )
(property "Value" "SYS_V" (id 1) (at 245.2371 80.0351 0) (property "Value" "SYS_V" (id 1) (at 245.2371 80.0351 0)
@@ -1454,7 +1454,7 @@
(symbol (lib_id "power:GND") (at 74.93 102.87 0) (symbol (lib_id "power:GND") (at 74.93 102.87 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid b7933d48-0da0-40fa-add8-8ea912a2dd50) (uuid b7933d48-0da0-40fa-add8-8ea912a2dd50)
(property "Reference" "#PWR0152" (id 0) (at 74.93 109.22 0) (property "Reference" "#PWR053" (id 0) (at 74.93 109.22 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Value" "GND" (id 1) (at 74.93 107.4326 0) (property "Value" "GND" (id 1) (at 74.93 107.4326 0)
@@ -1472,7 +1472,7 @@
(symbol (lib_id "power:GND") (at 83.82 102.87 0) (symbol (lib_id "power:GND") (at 83.82 102.87 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 1d025b1e-3f26-4ccc-8f66-e711501a4a4e) (uuid 1d025b1e-3f26-4ccc-8f66-e711501a4a4e)
(property "Reference" "#PWR0153" (id 0) (at 83.82 109.22 0) (property "Reference" "#PWR054" (id 0) (at 83.82 109.22 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Value" "GND" (id 1) (at 83.82 107.4326 0) (property "Value" "GND" (id 1) (at 83.82 107.4326 0)
@@ -1490,7 +1490,7 @@
(symbol (lib_id "power:GND") (at 123.19 105.41 0) (symbol (lib_id "power:GND") (at 123.19 105.41 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 9b880113-6c29-43d4-8b29-f279bec5a40c) (uuid 9b880113-6c29-43d4-8b29-f279bec5a40c)
(property "Reference" "#PWR0154" (id 0) (at 123.19 111.76 0) (property "Reference" "#PWR055" (id 0) (at 123.19 111.76 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Value" "GND" (id 1) (at 123.19 109.9726 0) (property "Value" "GND" (id 1) (at 123.19 109.9726 0)
@@ -1508,7 +1508,7 @@
(symbol (lib_id "power:GND") (at 138.43 105.41 0) (symbol (lib_id "power:GND") (at 138.43 105.41 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid a3ba886c-c63b-49e0-9eab-e7b978d5a054) (uuid a3ba886c-c63b-49e0-9eab-e7b978d5a054)
(property "Reference" "#PWR0155" (id 0) (at 138.43 111.76 0) (property "Reference" "#PWR056" (id 0) (at 138.43 111.76 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Value" "GND" (id 1) (at 138.43 109.9726 0) (property "Value" "GND" (id 1) (at 138.43 109.9726 0)
@@ -1526,7 +1526,7 @@
(symbol (lib_id "power:GND") (at 179.07 80.01 0) (symbol (lib_id "power:GND") (at 179.07 80.01 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 992969a7-0484-4581-b76d-d87466037767) (uuid 992969a7-0484-4581-b76d-d87466037767)
(property "Reference" "#PWR0156" (id 0) (at 179.07 86.36 0) (property "Reference" "#PWR057" (id 0) (at 179.07 86.36 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Value" "GND" (id 1) (at 179.07 84.5726 0) (property "Value" "GND" (id 1) (at 179.07 84.5726 0)
@@ -1544,7 +1544,7 @@
(symbol (lib_id "power:GND") (at 184.15 67.31 0) (symbol (lib_id "power:GND") (at 184.15 67.31 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid cc868e24-ef6a-458c-8b2c-f627d0a7263f) (uuid cc868e24-ef6a-458c-8b2c-f627d0a7263f)
(property "Reference" "#PWR0157" (id 0) (at 184.15 73.66 0) (property "Reference" "#PWR058" (id 0) (at 184.15 73.66 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Value" "GND" (id 1) (at 184.15 71.8726 0) (property "Value" "GND" (id 1) (at 184.15 71.8726 0)
@@ -1562,7 +1562,7 @@
(symbol (lib_id "power:GND") (at 185.42 125.73 0) (symbol (lib_id "power:GND") (at 185.42 125.73 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid bfe7ccce-845b-4a36-8ca2-eefe5a9b6211) (uuid bfe7ccce-845b-4a36-8ca2-eefe5a9b6211)
(property "Reference" "#PWR0158" (id 0) (at 185.42 132.08 0) (property "Reference" "#PWR059" (id 0) (at 185.42 132.08 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Value" "GND" (id 1) (at 185.42 130.2926 0) (property "Value" "GND" (id 1) (at 185.42 130.2926 0)
@@ -1580,7 +1580,7 @@
(symbol (lib_id "power:GND") (at 189.23 125.73 0) (symbol (lib_id "power:GND") (at 189.23 125.73 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 1cc197f2-039b-4b4b-aae4-8f72529a265a) (uuid 1cc197f2-039b-4b4b-aae4-8f72529a265a)
(property "Reference" "#PWR0159" (id 0) (at 189.23 132.08 0) (property "Reference" "#PWR060" (id 0) (at 189.23 132.08 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Value" "GND" (id 1) (at 189.23 130.2926 0) (property "Value" "GND" (id 1) (at 189.23 130.2926 0)
@@ -1598,7 +1598,7 @@
(symbol (lib_id "power:GND") (at 200.66 123.19 0) (symbol (lib_id "power:GND") (at 200.66 123.19 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 27c71f86-23d0-4bf2-9ffc-d740271a6344) (uuid 27c71f86-23d0-4bf2-9ffc-d740271a6344)
(property "Reference" "#PWR0160" (id 0) (at 200.66 129.54 0) (property "Reference" "#PWR061" (id 0) (at 200.66 129.54 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Value" "GND" (id 1) (at 200.66 127.7526 0) (property "Value" "GND" (id 1) (at 200.66 127.7526 0)
@@ -1616,7 +1616,7 @@
(symbol (lib_id "power:GND") (at 214.63 74.93 0) (symbol (lib_id "power:GND") (at 214.63 74.93 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 00f581de-2b04-42fd-b4a3-62d3dda6baf0) (uuid 00f581de-2b04-42fd-b4a3-62d3dda6baf0)
(property "Reference" "#PWR0161" (id 0) (at 214.63 81.28 0) (property "Reference" "#PWR062" (id 0) (at 214.63 81.28 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Value" "GND" (id 1) (at 214.63 79.4926 0) (property "Value" "GND" (id 1) (at 214.63 79.4926 0)
@@ -1634,7 +1634,7 @@
(symbol (lib_id "Device:R") (at 97.79 90.17 0) (symbol (lib_id "Device:R") (at 97.79 90.17 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid c86948ea-f0aa-4782-a2ae-156c62e49f88) (uuid c86948ea-f0aa-4782-a2ae-156c62e49f88)
(property "Reference" "R55" (id 0) (at 99.5681 89.2615 0) (property "Reference" "R14" (id 0) (at 99.5681 89.2615 0)
(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
) )
(property "Value" "1M" (id 1) (at 99.5681 92.0366 0) (property "Value" "1M" (id 1) (at 99.5681 92.0366 0)
@@ -1653,7 +1653,7 @@
(symbol (lib_id "Device:R") (at 123.19 101.6 0) (symbol (lib_id "Device:R") (at 123.19 101.6 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid e50a69a7-5d81-4684-90be-9b90cbfa951b) (uuid e50a69a7-5d81-4684-90be-9b90cbfa951b)
(property "Reference" "R56" (id 0) (at 124.9681 100.6915 0) (property "Reference" "R15" (id 0) (at 124.9681 100.6915 0)
(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
) )
(property "Value" "1M" (id 1) (at 124.9681 103.4666 0) (property "Value" "1M" (id 1) (at 124.9681 103.4666 0)
@@ -1672,7 +1672,7 @@
(symbol (lib_id "Device:R") (at 148.59 102.87 90) (symbol (lib_id "Device:R") (at 148.59 102.87 90)
(in_bom yes) (on_board yes) (in_bom yes) (on_board yes)
(uuid 6df0c01d-97b5-4180-a4da-bbb0ebd6edf6) (uuid 6df0c01d-97b5-4180-a4da-bbb0ebd6edf6)
(property "Reference" "R57" (id 0) (at 148.59 100.4274 90)) (property "Reference" "R16" (id 0) (at 148.59 100.4274 90))
(property "Value" "1.45M" (id 1) (at 148.59 105.7425 90)) (property "Value" "1.45M" (id 1) (at 148.59 105.7425 90))
(property "Footprint" "TCY_passives:R_0603_1608Metric" (id 2) (at 148.59 104.648 90) (property "Footprint" "TCY_passives:R_0603_1608Metric" (id 2) (at 148.59 104.648 90)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
@@ -1687,7 +1687,7 @@
(symbol (lib_id "Device:R") (at 156.21 106.68 90) (symbol (lib_id "Device:R") (at 156.21 106.68 90)
(in_bom yes) (on_board yes) (in_bom yes) (on_board yes)
(uuid 249de1af-fbbc-43fc-98ad-18432cf701ea) (uuid 249de1af-fbbc-43fc-98ad-18432cf701ea)
(property "Reference" "R58" (id 0) (at 156.21 104.2374 90)) (property "Reference" "R17" (id 0) (at 156.21 104.2374 90))
(property "Value" "18k" (id 1) (at 156.21 109.5525 90)) (property "Value" "18k" (id 1) (at 156.21 109.5525 90))
(property "Footprint" "TCY_passives:R_0603_1608Metric" (id 2) (at 156.21 108.458 90) (property "Footprint" "TCY_passives:R_0603_1608Metric" (id 2) (at 156.21 108.458 90)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
@@ -1702,7 +1702,7 @@
(symbol (lib_id "Device:R") (at 163.83 110.49 90) (symbol (lib_id "Device:R") (at 163.83 110.49 90)
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(uuid ef60402b-3865-4583-b55e-47a28740c59c) (uuid ef60402b-3865-4583-b55e-47a28740c59c)
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(property "Value" "169k" (id 1) (at 163.83 113.3625 90)) (property "Value" "169k" (id 1) (at 163.83 113.3625 90))
(property "Footprint" "TCY_passives:R_0603_1608Metric" (id 2) (at 163.83 112.268 90) (property "Footprint" "TCY_passives:R_0603_1608Metric" (id 2) (at 163.83 112.268 90)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
@@ -1717,7 +1717,7 @@
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(uuid 05cf8373-2a83-4c9f-9c4b-799fe2da0a0c) (uuid 05cf8373-2a83-4c9f-9c4b-799fe2da0a0c)
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(property "Value" "20mR" (id 1) (at 167.64 79.0725 90)) (property "Value" "20mR" (id 1) (at 167.64 79.0725 90))
(property "Footprint" "Resistor_SMD:R_2010_5025Metric" (id 2) (at 167.64 83.058 90) (property "Footprint" "Resistor_SMD:R_2010_5025Metric" (id 2) (at 167.64 83.058 90)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
@@ -1732,7 +1732,7 @@
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(uuid d8bb5cfa-4c99-4061-ac7e-761c6ef34017) (uuid d8bb5cfa-4c99-4061-ac7e-761c6ef34017)
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(property "Value" "20mR" (id 1) (at 167.64 91.7725 90)) (property "Value" "20mR" (id 1) (at 167.64 91.7725 90))
(property "Footprint" "Resistor_SMD:R_2010_5025Metric" (id 2) (at 167.64 88.138 90) (property "Footprint" "Resistor_SMD:R_2010_5025Metric" (id 2) (at 167.64 88.138 90)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
@@ -1747,7 +1747,7 @@
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(uuid 150ee852-43e1-4873-be33-1f0fa9887faf) (uuid 150ee852-43e1-4873-be33-1f0fa9887faf)
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(property "Value" "361k" (id 1) (at 171.45 117.1725 90)) (property "Value" "361k" (id 1) (at 171.45 117.1725 90))
(property "Footprint" "TCY_passives:R_0603_1608Metric" (id 2) (at 171.45 116.078 90) (property "Footprint" "TCY_passives:R_0603_1608Metric" (id 2) (at 171.45 116.078 90)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
@@ -1762,7 +1762,7 @@
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(uuid 3316e2ae-499a-4878-a3a3-39fbb809c686) (uuid 3316e2ae-499a-4878-a3a3-39fbb809c686)
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(property "Value" "100k" (id 1) (at 195.58 70.1825 90)) (property "Value" "100k" (id 1) (at 195.58 70.1825 90))
(property "Footprint" "TCY_passives:R_0603_1608Metric" (id 2) (at 195.58 74.168 90) (property "Footprint" "TCY_passives:R_0603_1608Metric" (id 2) (at 195.58 74.168 90)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
@@ -1777,7 +1777,7 @@
(symbol (lib_id "Device:R") (at 208.28 72.39 90) (symbol (lib_id "Device:R") (at 208.28 72.39 90)
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(property "Reference" "R64" (id 0) (at 208.28 67.4074 90)) (property "Reference" "R23" (id 0) (at 208.28 67.4074 90))
(property "Value" "270k" (id 1) (at 208.28 70.1825 90)) (property "Value" "270k" (id 1) (at 208.28 70.1825 90))
(property "Footprint" "TCY_passives:R_0603_1608Metric" (id 2) (at 208.28 74.168 90) (property "Footprint" "TCY_passives:R_0603_1608Metric" (id 2) (at 208.28 74.168 90)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
@@ -1792,7 +1792,7 @@
(symbol (lib_id "Device:R") (at 231.14 95.25 0) (symbol (lib_id "Device:R") (at 231.14 95.25 0)
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(uuid 07440c69-9ed8-4cd1-8b3f-30cd1be833b3) (uuid 07440c69-9ed8-4cd1-8b3f-30cd1be833b3)
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(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
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(property "Value" "20k" (id 1) (at 232.9181 97.1166 0) (property "Value" "20k" (id 1) (at 232.9181 97.1166 0)
@@ -1811,7 +1811,7 @@
(symbol (lib_id "Device:D_TVS") (at 138.43 92.71 90) (symbol (lib_id "Device:D_TVS") (at 138.43 92.71 90)
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(uuid afa7b511-6607-4999-85d4-65f661342542) (uuid afa7b511-6607-4999-85d4-65f661342542)
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(effects (font (size 1.27 1.27)) (justify right)) (effects (font (size 1.27 1.27)) (justify right))
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(property "Value" "5V" (id 1) (at 140.4367 94.5766 90) (property "Value" "5V" (id 1) (at 140.4367 94.5766 90)
@@ -1830,7 +1830,7 @@
(symbol (lib_id "Device:D_Zener") (at 208.28 53.34 0) (symbol (lib_id "Device:D_Zener") (at 208.28 53.34 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
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(property "Value" "3V3" (id 1) (at 208.28 50.9039 0)) (property "Value" "3V3" (id 1) (at 208.28 50.9039 0))
(property "Footprint" "Diode_SMD:D_SOD-323F" (id 2) (at 208.28 53.34 0) (property "Footprint" "Diode_SMD:D_SOD-323F" (id 2) (at 208.28 53.34 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
@@ -1845,7 +1845,7 @@
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(property "Value" "100nF" (id 1) (at 66.4211 97.1166 0) (property "Value" "100nF" (id 1) (at 66.4211 97.1166 0)
@@ -1864,7 +1864,7 @@
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@@ -1883,7 +1883,7 @@
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(property "Value" "10nF" (id 1) (at 208.28 60.1495 90)) (property "Value" "10nF" (id 1) (at 208.28 60.1495 90))
(property "Footprint" "TCY_passives:C_0603_1608Metric" (id 2) (at 212.09 62.5348 0) (property "Footprint" "TCY_passives:C_0603_1608Metric" (id 2) (at 212.09 62.5348 0)
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@@ -1898,7 +1898,7 @@
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(property "Value" "DMP21D6UFD" (id 1) (at 106.8071 98.3866 0) (property "Value" "DMP21D6UFD" (id 1) (at 106.8071 98.3866 0)
@@ -1918,7 +1918,7 @@
(symbol (lib_id "TCY_transistors:SiS413DN") (at 129.54 83.82 270) (mirror x) (symbol (lib_id "TCY_transistors:SiS413DN") (at 129.54 83.82 270) (mirror x)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
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(effects (font (size 1 1))) (effects (font (size 1 1)))
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(property "Value" "SiS413DN" (id 1) (at 129.54 80.7878 90) (property "Value" "SiS413DN" (id 1) (at 129.54 80.7878 90)
@@ -1940,7 +1940,7 @@
(symbol (lib_id "TCY_transistors:SiSA96DDN") (at 208.28 86.36 90) (symbol (lib_id "TCY_transistors:SiSA96DDN") (at 208.28 86.36 90)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
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(effects (font (size 1 1))) (effects (font (size 1 1)))
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(property "Value" "SiSA96DDN" (id 1) (at 208.28 80.7878 90) (property "Value" "SiSA96DDN" (id 1) (at 208.28 80.7878 90)
@@ -1962,7 +1962,7 @@
(symbol (lib_id "TCY_transistors:SiSA96DDN") (at 223.52 86.36 270) (mirror x) (symbol (lib_id "TCY_transistors:SiSA96DDN") (at 223.52 86.36 270) (mirror x)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 09031a18-3d44-41b6-8838-4c9fa86fa436) (uuid 09031a18-3d44-41b6-8838-4c9fa86fa436)
(property "Reference" "Q16" (id 0) (at 223.52 78.5488 90) (property "Reference" "Q8" (id 0) (at 223.52 78.5488 90)
(effects (font (size 1 1))) (effects (font (size 1 1)))
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(property "Value" "SiSA96DDN" (id 1) (at 223.52 80.7878 90) (property "Value" "SiSA96DDN" (id 1) (at 223.52 80.7878 90)
@@ -1984,7 +1984,7 @@
(symbol (lib_id "Power_Management:BD49xxFVE") (at 83.82 95.25 0) (symbol (lib_id "Power_Management:BD49xxFVE") (at 83.82 95.25 0)
(in_bom yes) (on_board yes) (in_bom yes) (on_board yes)
(uuid 6de8822c-c6ea-495e-95e1-d8df9370c33b) (uuid 6de8822c-c6ea-495e-95e1-d8df9370c33b)
(property "Reference" "U16" (id 0) (at 95.7579 100.6915 0) (property "Reference" "U3" (id 0) (at 95.7579 100.6915 0)
(effects (font (size 1.27 1.27)) (justify right)) (effects (font (size 1.27 1.27)) (justify right))
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(property "Value" "BD49xxFVE" (id 1) (at 97.0279 103.4666 0) (property "Value" "BD49xxFVE" (id 1) (at 97.0279 103.4666 0)
@@ -2005,7 +2005,7 @@
(symbol (lib_id "TCY_power_management:INA199") (at 181.61 72.39 0) (symbol (lib_id "TCY_power_management:INA199") (at 181.61 72.39 0)
(in_bom yes) (on_board yes) (in_bom yes) (on_board yes)
(uuid 80b279ee-9f1a-4bfe-b9b7-434efc346219) (uuid 80b279ee-9f1a-4bfe-b9b7-434efc346219)
(property "Reference" "U17" (id 0) (at 185.1661 77.8315 0) (property "Reference" "U4" (id 0) (at 185.1661 77.8315 0)
(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
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(property "Value" "INA199x1" (id 1) (at 185.1661 75.5266 0) (property "Value" "INA199x1" (id 1) (at 185.1661 75.5266 0)
@@ -2030,7 +2030,7 @@
(symbol (lib_id "TCY_power_management:LTC4231") (at 186.69 105.41 0) (symbol (lib_id "TCY_power_management:LTC4231") (at 186.69 105.41 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 41c6c7f0-65e9-418c-9e52-ea431c581b1b) (uuid 41c6c7f0-65e9-418c-9e52-ea431c581b1b)
(property "Reference" "U18" (id 0) (at 186.69 86.2034 0)) (property "Reference" "U5" (id 0) (at 186.69 86.2034 0))
(property "Value" "LTC4231" (id 1) (at 186.69 88.9785 0)) (property "Value" "LTC4231" (id 1) (at 186.69 88.9785 0))
(property "Footprint" "Package_DFN_QFN:QFN-12-1EP_3x3mm_P0.5mm_EP1.65x1.65mm_ThermalVias" (id 2) (at 186.69 143.51 0) (property "Footprint" "Package_DFN_QFN:QFN-12-1EP_3x3mm_P0.5mm_EP1.65x1.65mm_ThermalVias" (id 2) (at 186.69 143.51 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
+8 -8
View File
@@ -700,7 +700,7 @@
(symbol (lib_id "power:PWR_FLAG") (at 198.12 105.41 0) (symbol (lib_id "power:PWR_FLAG") (at 198.12 105.41 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid c8253c12-cea3-490b-9399-c0ed3af2f13e) (uuid c8253c12-cea3-490b-9399-c0ed3af2f13e)
(property "Reference" "#FLG032" (id 0) (at 198.12 103.505 0) (property "Reference" "#FLG031" (id 0) (at 198.12 103.505 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
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(property "Value" "PWR_FLAG" (id 1) (at 198.12 101.8054 0)) (property "Value" "PWR_FLAG" (id 1) (at 198.12 101.8054 0))
@@ -752,7 +752,7 @@
(symbol (lib_id "power:GND") (at 121.92 80.01 0) (symbol (lib_id "power:GND") (at 121.92 80.01 0)
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(uuid ee475694-3da4-4ade-9d58-3b473d12d511) (uuid ee475694-3da4-4ade-9d58-3b473d12d511)
(property "Reference" "#PWR0274" (id 0) (at 121.92 86.36 0) (property "Reference" "#PWR0267" (id 0) (at 121.92 86.36 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
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(property "Value" "GND" (id 1) (at 121.92 84.5726 0) (property "Value" "GND" (id 1) (at 121.92 84.5726 0)
@@ -770,7 +770,7 @@
(symbol (lib_id "power:GND") (at 143.51 86.36 0) (symbol (lib_id "power:GND") (at 143.51 86.36 0)
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(uuid 4373c2a8-a1ca-4c96-9e11-fbb53bbc7fba) (uuid 4373c2a8-a1ca-4c96-9e11-fbb53bbc7fba)
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(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
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(property "Value" "GND" (id 1) (at 143.51 90.9226 0) (property "Value" "GND" (id 1) (at 143.51 90.9226 0)
@@ -788,7 +788,7 @@
(symbol (lib_id "power:GND") (at 148.59 72.39 0) (symbol (lib_id "power:GND") (at 148.59 72.39 0)
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(uuid 29977e9b-4a0d-4a9f-9cc6-fb5f61fe96ef) (uuid 29977e9b-4a0d-4a9f-9cc6-fb5f61fe96ef)
(property "Reference" "#PWR0276" (id 0) (at 148.59 78.74 0) (property "Reference" "#PWR0269" (id 0) (at 148.59 78.74 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
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(property "Value" "GND" (id 1) (at 148.59 76.9526 0) (property "Value" "GND" (id 1) (at 148.59 76.9526 0)
@@ -806,7 +806,7 @@
(symbol (lib_id "power:GND") (at 156.21 123.19 0) (symbol (lib_id "power:GND") (at 156.21 123.19 0)
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(uuid 22c15bb5-f31e-4dea-aea6-ae0d3261e290) (uuid 22c15bb5-f31e-4dea-aea6-ae0d3261e290)
(property "Reference" "#PWR0277" (id 0) (at 156.21 129.54 0) (property "Reference" "#PWR0270" (id 0) (at 156.21 129.54 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
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(property "Value" "GND" (id 1) (at 156.21 127.7526 0) (property "Value" "GND" (id 1) (at 156.21 127.7526 0)
@@ -824,7 +824,7 @@
(symbol (lib_id "power:GND") (at 157.48 96.52 0) (symbol (lib_id "power:GND") (at 157.48 96.52 0)
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(uuid 46ae66f1-57f5-45d5-838f-3766d3ccf8f6) (uuid 46ae66f1-57f5-45d5-838f-3766d3ccf8f6)
(property "Reference" "#PWR0278" (id 0) (at 157.48 102.87 0) (property "Reference" "#PWR0271" (id 0) (at 157.48 102.87 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
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(property "Value" "GND" (id 1) (at 157.48 101.0826 0) (property "Value" "GND" (id 1) (at 157.48 101.0826 0)
@@ -842,7 +842,7 @@
(symbol (lib_id "power:GND") (at 166.37 96.52 0) (symbol (lib_id "power:GND") (at 166.37 96.52 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 737db744-b62d-49f0-8401-672c12195c89) (uuid 737db744-b62d-49f0-8401-672c12195c89)
(property "Reference" "#PWR0279" (id 0) (at 166.37 102.87 0) (property "Reference" "#PWR0272" (id 0) (at 166.37 102.87 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Value" "GND" (id 1) (at 166.37 101.0826 0) (property "Value" "GND" (id 1) (at 166.37 101.0826 0)
@@ -860,7 +860,7 @@
(symbol (lib_id "power:GND") (at 175.26 96.52 0) (symbol (lib_id "power:GND") (at 175.26 96.52 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 0ea567c7-6e39-4188-9b81-5675115b0a6b) (uuid 0ea567c7-6e39-4188-9b81-5675115b0a6b)
(property "Reference" "#PWR0280" (id 0) (at 175.26 102.87 0) (property "Reference" "#PWR0273" (id 0) (at 175.26 102.87 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Value" "GND" (id 1) (at 175.26 101.0826 0) (property "Value" "GND" (id 1) (at 175.26 101.0826 0)
+43
View File
@@ -13,6 +13,32 @@
) )
(lib_symbols (lib_symbols
(symbol "Mechanical:MountingHole" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
(property "Reference" "H" (id 0) (at 0 5.08 0)
(effects (font (size 1.27 1.27)))
)
(property "Value" "MountingHole" (id 1) (at 0 3.175 0)
(effects (font (size 1.27 1.27)))
)
(property "Footprint" "" (id 2) (at 0 0 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "~" (id 3) (at 0 0 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "ki_keywords" "mounting hole" (id 4) (at 0 0 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "ki_description" "Mounting Hole without connection" (id 5) (at 0 0 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "ki_fp_filters" "MountingHole*" (id 6) (at 0 0 0)
(effects (font (size 1.27 1.27)) hide)
)
(symbol "MountingHole_0_1"
(circle (center 0 0) (radius 1.27) (stroke (width 1.27)) (fill (type none)))
)
)
) )
(junction (at 99.06 72.39) (diameter 1.016) (color 0 0 0 0)) (junction (at 99.06 72.39) (diameter 1.016) (color 0 0 0 0))
@@ -188,6 +214,23 @@
(uuid fe43b749-8a0a-4eb8-b44f-3137985cebb9) (uuid fe43b749-8a0a-4eb8-b44f-3137985cebb9)
) )
(symbol (lib_id "Mechanical:MountingHole") (at 262.89 158.75 0)
(in_bom yes) (on_board yes) (fields_autoplaced)
(uuid bcb184fa-cb43-4f8a-880d-f0338c82df5f)
(property "Reference" "H7" (id 0) (at 265.4301 157.8415 0)
(effects (font (size 1.27 1.27)) (justify left))
)
(property "Value" "MountingHole" (id 1) (at 265.4301 160.6166 0)
(effects (font (size 1.27 1.27)) (justify left))
)
(property "Footprint" "MountingHole:MountingHole_3.2mm_M3_Pad_Via" (id 2) (at 262.89 158.75 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "~" (id 3) (at 262.89 158.75 0)
(effects (font (size 1.27 1.27)) hide)
)
)
(sheet (at 113.03 27.94) (size 33.02 20.32) (fields_autoplaced) (sheet (at 113.03 27.94) (size 33.02 20.32) (fields_autoplaced)
(stroke (width 0.001) (type solid) (color 132 0 132 1)) (stroke (width 0.001) (type solid) (color 132 0 132 1))
(fill (color 72 72 72 1.0000)) (fill (color 72 72 72 1.0000))
+22 -22
View File
@@ -1076,7 +1076,7 @@
(symbol (lib_id "Connector:TestPoint") (at 153.67 88.9 0) (symbol (lib_id "Connector:TestPoint") (at 153.67 88.9 0)
(in_bom yes) (on_board yes) (in_bom yes) (on_board yes)
(uuid bd290f96-4ed3-449c-a9a9-5e397d65f6c5) (uuid bd290f96-4ed3-449c-a9a9-5e397d65f6c5)
(property "Reference" "TP51" (id 0) (at 152.5271 79.8 0) (property "Reference" "TP54" (id 0) (at 152.5271 79.8 0)
(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
) )
(property "Value" "SOURCE_V" (id 1) (at 152.5271 82.5751 0) (property "Value" "SOURCE_V" (id 1) (at 152.5271 82.5751 0)
@@ -1094,7 +1094,7 @@
(symbol (lib_id "Connector:TestPoint") (at 208.28 71.12 0) (symbol (lib_id "Connector:TestPoint") (at 208.28 71.12 0)
(in_bom yes) (on_board yes) (in_bom yes) (on_board yes)
(uuid 12219d6e-5aac-42c8-a90c-26e3f83d4257) (uuid 12219d6e-5aac-42c8-a90c-26e3f83d4257)
(property "Reference" "TP52" (id 0) (at 207.1371 62.02 0) (property "Reference" "TP55" (id 0) (at 207.1371 62.02 0)
(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
) )
(property "Value" "SOURCE_I" (id 1) (at 207.1371 64.7951 0) (property "Value" "SOURCE_I" (id 1) (at 207.1371 64.7951 0)
@@ -1112,7 +1112,7 @@
(symbol (lib_id "Connector:TestPoint") (at 228.6 88.9 0) (symbol (lib_id "Connector:TestPoint") (at 228.6 88.9 0)
(in_bom yes) (on_board yes) (in_bom yes) (on_board yes)
(uuid 8d6509b2-e2f4-43f1-82be-30ba7bf064fe) (uuid 8d6509b2-e2f4-43f1-82be-30ba7bf064fe)
(property "Reference" "TP53" (id 0) (at 227.4571 79.8 0) (property "Reference" "TP56" (id 0) (at 227.4571 79.8 0)
(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
) )
(property "Value" "SOURCE_OUT" (id 1) (at 227.4571 82.5751 0) (property "Value" "SOURCE_OUT" (id 1) (at 227.4571 82.5751 0)
@@ -1346,7 +1346,7 @@
(symbol (lib_id "Device:L") (at 124.46 74.93 90) (symbol (lib_id "Device:L") (at 124.46 74.93 90)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid c61284fb-b235-43b0-b218-8bc6019b60e1) (uuid c61284fb-b235-43b0-b218-8bc6019b60e1)
(property "Reference" "L7" (id 0) (at 124.46 70.4554 90)) (property "Reference" "L8" (id 0) (at 124.46 70.4554 90))
(property "Value" "2.2uH" (id 1) (at 124.46 73.2305 90)) (property "Value" "2.2uH" (id 1) (at 124.46 73.2305 90))
(property "Footprint" "Inductor_SMD:L_Taiyo-Yuden_MD-5050" (id 2) (at 124.46 74.93 0) (property "Footprint" "Inductor_SMD:L_Taiyo-Yuden_MD-5050" (id 2) (at 124.46 74.93 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
@@ -1361,7 +1361,7 @@
(symbol (lib_id "Device:R") (at 102.87 93.98 0) (symbol (lib_id "Device:R") (at 102.87 93.98 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 3089d219-f91c-4780-bdaa-196ebbdedf87) (uuid 3089d219-f91c-4780-bdaa-196ebbdedf87)
(property "Reference" "R115" (id 0) (at 104.6481 93.0715 0) (property "Reference" "R122" (id 0) (at 104.6481 93.0715 0)
(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
) )
(property "Value" "100R" (id 1) (at 104.6481 95.8466 0) (property "Value" "100R" (id 1) (at 104.6481 95.8466 0)
@@ -1380,7 +1380,7 @@
(symbol (lib_id "Device:R") (at 143.51 93.98 0) (symbol (lib_id "Device:R") (at 143.51 93.98 0)
(in_bom yes) (on_board yes) (in_bom yes) (on_board yes)
(uuid 9b169cde-1701-4a15-a018-14af55b54a2b) (uuid 9b169cde-1701-4a15-a018-14af55b54a2b)
(property "Reference" "R116" (id 0) (at 145.2881 94.3415 0) (property "Reference" "R123" (id 0) (at 145.2881 94.3415 0)
(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
) )
(property "Value" "520k/1.12M/1.8M" (id 1) (at 145.2881 92.0366 0) (property "Value" "520k/1.12M/1.8M" (id 1) (at 145.2881 92.0366 0)
@@ -1399,7 +1399,7 @@
(symbol (lib_id "Device:R") (at 143.51 114.3 0) (symbol (lib_id "Device:R") (at 143.51 114.3 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid edb34068-00d6-4168-b744-075735693e81) (uuid edb34068-00d6-4168-b744-075735693e81)
(property "Reference" "R117" (id 0) (at 145.2881 113.3915 0) (property "Reference" "R124" (id 0) (at 145.2881 113.3915 0)
(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
) )
(property "Value" "200k" (id 1) (at 145.2881 116.1666 0) (property "Value" "200k" (id 1) (at 145.2881 116.1666 0)
@@ -1418,7 +1418,7 @@
(symbol (lib_id "Device:R") (at 176.53 88.9 90) (symbol (lib_id "Device:R") (at 176.53 88.9 90)
(in_bom yes) (on_board yes) (in_bom yes) (on_board yes)
(uuid 57ee2ae8-39d7-4647-b4db-5919a1cac11f) (uuid 57ee2ae8-39d7-4647-b4db-5919a1cac11f)
(property "Reference" "R118" (id 0) (at 176.53 83.9174 90)) (property "Reference" "R125" (id 0) (at 176.53 83.9174 90))
(property "Value" "20mR" (id 1) (at 176.53 86.6925 90)) (property "Value" "20mR" (id 1) (at 176.53 86.6925 90))
(property "Footprint" "Resistor_SMD:R_2010_5025Metric" (id 2) (at 176.53 90.678 90) (property "Footprint" "Resistor_SMD:R_2010_5025Metric" (id 2) (at 176.53 90.678 90)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
@@ -1433,7 +1433,7 @@
(symbol (lib_id "Device:R") (at 200.66 66.04 180) (symbol (lib_id "Device:R") (at 200.66 66.04 180)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 4b5d3980-caa6-4341-a4be-95f6ac170448) (uuid 4b5d3980-caa6-4341-a4be-95f6ac170448)
(property "Reference" "R119" (id 0) (at 202.4381 65.1315 0) (property "Reference" "R126" (id 0) (at 202.4381 65.1315 0)
(effects (font (size 1.27 1.27)) (justify right)) (effects (font (size 1.27 1.27)) (justify right))
) )
(property "Value" "100k" (id 1) (at 202.4381 67.9066 0) (property "Value" "100k" (id 1) (at 202.4381 67.9066 0)
@@ -1452,7 +1452,7 @@
(symbol (lib_id "Device:R") (at 200.66 76.2 180) (symbol (lib_id "Device:R") (at 200.66 76.2 180)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 0e8425b5-7118-43f0-9262-10ddb2e80139) (uuid 0e8425b5-7118-43f0-9262-10ddb2e80139)
(property "Reference" "R120" (id 0) (at 202.4381 75.2915 0) (property "Reference" "R127" (id 0) (at 202.4381 75.2915 0)
(effects (font (size 1.27 1.27)) (justify right)) (effects (font (size 1.27 1.27)) (justify right))
) )
(property "Value" "270k" (id 1) (at 202.4381 78.0666 0) (property "Value" "270k" (id 1) (at 202.4381 78.0666 0)
@@ -1471,7 +1471,7 @@
(symbol (lib_id "Device:R") (at 203.2 102.87 0) (symbol (lib_id "Device:R") (at 203.2 102.87 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 08f809c6-2d77-40c1-b3e6-711475598559) (uuid 08f809c6-2d77-40c1-b3e6-711475598559)
(property "Reference" "R121" (id 0) (at 204.9781 101.9615 0) (property "Reference" "R128" (id 0) (at 204.9781 101.9615 0)
(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
) )
(property "Value" "1M" (id 1) (at 204.9781 104.7366 0) (property "Value" "1M" (id 1) (at 204.9781 104.7366 0)
@@ -1490,7 +1490,7 @@
(symbol (lib_id "Device:D_Zener") (at 208.28 76.2 270) (symbol (lib_id "Device:D_Zener") (at 208.28 76.2 270)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 2c3e2eec-bef4-4877-be07-97d3b7318dc5) (uuid 2c3e2eec-bef4-4877-be07-97d3b7318dc5)
(property "Reference" "D17" (id 0) (at 210.2867 75.2915 90) (property "Reference" "D18" (id 0) (at 210.2867 75.2915 90)
(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
) )
(property "Value" "3V3" (id 1) (at 210.2867 78.0666 90) (property "Value" "3V3" (id 1) (at 210.2867 78.0666 90)
@@ -1509,7 +1509,7 @@
(symbol (lib_id "Device:Polyfuse") (at 217.17 88.9 90) (symbol (lib_id "Device:Polyfuse") (at 217.17 88.9 90)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 8e4adf92-49ad-4b97-a921-787246d814f0) (uuid 8e4adf92-49ad-4b97-a921-787246d814f0)
(property "Reference" "F11" (id 0) (at 217.17 83.5364 90)) (property "Reference" "F12" (id 0) (at 217.17 83.5364 90))
(property "Value" "2A" (id 1) (at 217.17 86.3115 90)) (property "Value" "2A" (id 1) (at 217.17 86.3115 90))
(property "Footprint" "Fuse:Fuse_1206_3216Metric" (id 2) (at 222.25 87.63 0) (property "Footprint" "Fuse:Fuse_1206_3216Metric" (id 2) (at 222.25 87.63 0)
(effects (font (size 1.27 1.27)) (justify left) hide) (effects (font (size 1.27 1.27)) (justify left) hide)
@@ -1524,7 +1524,7 @@
(symbol (lib_id "Device:C") (at 90.17 93.98 0) (symbol (lib_id "Device:C") (at 90.17 93.98 0)
(in_bom yes) (on_board yes) (in_bom yes) (on_board yes)
(uuid bf00f5b7-4b03-4b9b-9beb-c16b5285f72d) (uuid bf00f5b7-4b03-4b9b-9beb-c16b5285f72d)
(property "Reference" "C115" (id 0) (at 93.0911 94.3415 0) (property "Reference" "C120" (id 0) (at 93.0911 94.3415 0)
(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
) )
(property "Value" "10uF (X7R)" (id 1) (at 90.5511 97.1166 0) (property "Value" "10uF (X7R)" (id 1) (at 90.5511 97.1166 0)
@@ -1543,7 +1543,7 @@
(symbol (lib_id "Device:C") (at 102.87 104.14 0) (symbol (lib_id "Device:C") (at 102.87 104.14 0)
(in_bom yes) (on_board yes) (in_bom yes) (on_board yes)
(uuid 16350d36-21bf-4cb0-8481-d55787b39d40) (uuid 16350d36-21bf-4cb0-8481-d55787b39d40)
(property "Reference" "C116" (id 0) (at 94.3611 104.5015 0) (property "Reference" "C121" (id 0) (at 94.3611 104.5015 0)
(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
) )
(property "Value" "100nF (X7R)" (id 1) (at 89.2811 107.2766 0) (property "Value" "100nF (X7R)" (id 1) (at 89.2811 107.2766 0)
@@ -1562,7 +1562,7 @@
(symbol (lib_id "Device:C") (at 156.21 97.79 0) (symbol (lib_id "Device:C") (at 156.21 97.79 0)
(in_bom yes) (on_board yes) (in_bom yes) (on_board yes)
(uuid 8adec100-a1a6-41e4-b4a7-f3f3bc4b2ca1) (uuid 8adec100-a1a6-41e4-b4a7-f3f3bc4b2ca1)
(property "Reference" "C117" (id 0) (at 159.1311 98.1515 0) (property "Reference" "C122" (id 0) (at 159.1311 98.1515 0)
(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
) )
(property "Value" "10uF (X7R)" (id 1) (at 156.5911 100.9266 0) (property "Value" "10uF (X7R)" (id 1) (at 156.5911 100.9266 0)
@@ -1581,7 +1581,7 @@
(symbol (lib_id "Device:C") (at 165.1 59.69 0) (symbol (lib_id "Device:C") (at 165.1 59.69 0)
(in_bom yes) (on_board yes) (in_bom yes) (on_board yes)
(uuid 148c8ecd-04d2-4757-b5c0-9eee95504366) (uuid 148c8ecd-04d2-4757-b5c0-9eee95504366)
(property "Reference" "C118" (id 0) (at 156.5911 58.7815 0) (property "Reference" "C123" (id 0) (at 156.5911 58.7815 0)
(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
) )
(property "Value" "100nF" (id 1) (at 156.5911 61.5566 0) (property "Value" "100nF" (id 1) (at 156.5911 61.5566 0)
@@ -1600,7 +1600,7 @@
(symbol (lib_id "Device:C") (at 167.64 97.79 0) (symbol (lib_id "Device:C") (at 167.64 97.79 0)
(in_bom yes) (on_board yes) (in_bom yes) (on_board yes)
(uuid 73f3621e-3d60-498b-a529-65605fa975d8) (uuid 73f3621e-3d60-498b-a529-65605fa975d8)
(property "Reference" "C119" (id 0) (at 170.5611 98.1515 0) (property "Reference" "C124" (id 0) (at 170.5611 98.1515 0)
(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
) )
(property "Value" "10uF (X7R)" (id 1) (at 168.0211 100.9266 0) (property "Value" "10uF (X7R)" (id 1) (at 168.0211 100.9266 0)
@@ -1619,7 +1619,7 @@
(symbol (lib_id "Device:R_POT") (at 143.51 104.14 0) (symbol (lib_id "Device:R_POT") (at 143.51 104.14 0)
(in_bom yes) (on_board yes) (in_bom yes) (on_board yes)
(uuid a44da014-6bbf-4eff-aa85-6f77eb7124cc) (uuid a44da014-6bbf-4eff-aa85-6f77eb7124cc)
(property "Reference" "RV5" (id 0) (at 149.352 108.3115 0) (property "Reference" "RV6" (id 0) (at 149.352 108.3115 0)
(effects (font (size 1.27 1.27)) (justify right)) (effects (font (size 1.27 1.27)) (justify right))
) )
(property "Value" "100k" (id 1) (at 151.892 106.0066 0) (property "Value" "100k" (id 1) (at 151.892 106.0066 0)
@@ -1639,7 +1639,7 @@
(symbol (lib_id "TCY_transistors:SiS413DN") (at 203.2 88.9 270) (mirror x) (symbol (lib_id "TCY_transistors:SiS413DN") (at 203.2 88.9 270) (mirror x)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 86ba3151-bbed-4b81-b0fb-078cc537837a) (uuid 86ba3151-bbed-4b81-b0fb-078cc537837a)
(property "Reference" "Q25" (id 0) (at 203.2 83.6288 90) (property "Reference" "Q26" (id 0) (at 203.2 83.6288 90)
(effects (font (size 1 1))) (effects (font (size 1 1)))
) )
(property "Value" "SiS413DN" (id 1) (at 203.2 85.8678 90) (property "Value" "SiS413DN" (id 1) (at 203.2 85.8678 90)
@@ -1661,7 +1661,7 @@
(symbol (lib_id "TCY_power_management:INA199") (at 189.23 62.23 0) (symbol (lib_id "TCY_power_management:INA199") (at 189.23 62.23 0)
(in_bom yes) (on_board yes) (in_bom yes) (on_board yes)
(uuid 4c2ff129-ffc8-4675-931e-6350c72d635e) (uuid 4c2ff129-ffc8-4675-931e-6350c72d635e)
(property "Reference" "U42" (id 0) (at 186.4361 49.8915 0) (property "Reference" "U44" (id 0) (at 186.4361 49.8915 0)
(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
) )
(property "Value" "INA199x2" (id 1) (at 183.8961 52.6666 0) (property "Value" "INA199x2" (id 1) (at 183.8961 52.6666 0)
@@ -1686,7 +1686,7 @@
(symbol (lib_id "Regulator_Switching:TPS63000") (at 124.46 93.98 0) (symbol (lib_id "Regulator_Switching:TPS63000") (at 124.46 93.98 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 74694f0a-ece9-45a0-b17c-3004a870c052) (uuid 74694f0a-ece9-45a0-b17c-3004a870c052)
(property "Reference" "U41" (id 0) (at 124.46 77.3134 0)) (property "Reference" "U43" (id 0) (at 124.46 77.3134 0))
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(property "Footprint" "Package_SON:Texas_DRC0010J_ThermalVias" (id 2) (at 146.05 107.95 0) (property "Footprint" "Package_SON:Texas_DRC0010J_ThermalVias" (id 2) (at 146.05 107.95 0)
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View File
@@ -1,4 +1,4 @@
17065953200516631 17064322013153957
Battery Battery
BatteryHolder_Bulgin_BX0036_1xC BatteryHolder_Bulgin_BX0036_1xC
Bulgin Battery Holder, BX0036, Battery Type C (https://www.bulgin.com/products/pub/media/bulgin/data/Battery_holders.pdf) Bulgin Battery Holder, BX0036, Battery Type C (https://www.bulgin.com/products/pub/media/bulgin/data/Battery_holders.pdf)
@@ -70602,13 +70602,6 @@ capacitor
2 2
2 2
TCY_passives TCY_passives
D_0603_1608Metric
Diode SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator
diode
0
2
2
TCY_passives
RV_3x3.6 RV_3x3.6
-1
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@@ -1,2 +1 @@
Solar_module_XY-backups Solar_module_XY-backups
gerbers/
File diff suppressed because it is too large Load Diff
File diff suppressed because it is too large Load Diff
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@@ -55,40 +55,7 @@
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@@ -102,7 +69,6 @@
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@@ -121,7 +87,6 @@
"silk_over_copper": "error", "silk_over_copper": "error",
"silk_overlap": "error", "silk_overlap": "error",
"skew_out_of_range": "error", "skew_out_of_range": "error",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error", "too_many_vias": "error",
"track_dangling": "warning", "track_dangling": "warning",
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@@ -350,7 +315,6 @@
], ],
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@@ -407,7 +371,7 @@
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(rev "v1.0") (rev "v1.0")
(company "VUT") (company "VUT")
(comment 1 "Author: Petr Malaník") (comment 1 "Author: Petr Malaník")
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(stroke (width 0) (type solid) (color 0 0 0 0))
(uuid 887cbb09-1f15-43a8-acfc-207e7e7a34ba)
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(wire (pts (xy 105.41 104.14) (xy 128.27 104.14))
(stroke (width 0) (type solid) (color 0 0 0 0))
(uuid 887cbb09-1f15-43a8-acfc-207e7e7a34ba)
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(stroke (width 0) (type solid) (color 0 0 0 0)) (stroke (width 0) (type solid) (color 0 0 0 0))
@@ -325,7 +287,19 @@
) )
(wire (pts (xy 124.46 100.33) (xy 124.46 95.25)) (wire (pts (xy 124.46 100.33) (xy 124.46 95.25))
(stroke (width 0) (type solid) (color 0 0 0 0)) (stroke (width 0) (type solid) (color 0 0 0 0))
(uuid f6000d72-d9f2-447c-bfe6-6e5a597bebca) (uuid f6000d72-d9f2-447c-bfe6-6e5a597bebc9)
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(wire (pts (xy 128.27 90.17) (xy 123.19 90.17))
(stroke (width 0) (type solid) (color 0 0 0 0))
(uuid 887cbb09-1f15-43a8-acfc-207e7e7a34ba)
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(wire (pts (xy 128.27 90.17) (xy 134.62 90.17))
(stroke (width 0) (type solid) (color 0 0 0 0))
(uuid 7c5f2db0-21c3-45fc-bc73-ce414a62eb56)
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(wire (pts (xy 128.27 104.14) (xy 128.27 90.17))
(stroke (width 0) (type solid) (color 0 0 0 0))
(uuid 887cbb09-1f15-43a8-acfc-207e7e7a34ba)
) )
(hierarchical_label "OUT" (shape input) (at 134.62 90.17 0) (hierarchical_label "OUT" (shape input) (at 134.62 90.17 0)
@@ -333,47 +307,28 @@
(uuid 69e3588f-e815-46f8-b7ce-6f605a0c9e5c) (uuid 69e3588f-e815-46f8-b7ce-6f605a0c9e5c)
) )
(symbol (lib_id "Device:Solar_Cell") (at 85.09 106.68 0) (symbol (lib_id "power:GND") (at 85.09 109.22 0)
(in_bom yes) (on_board yes)
(uuid 0348ac21-372c-4d21-8b02-7758ba9a4bbd)
(property "Reference" "SC6" (id 0) (at 75.0571 104.6491 0)
(effects (font (size 1.27 1.27)) (justify left))
)
(property "Value" "SM141K04L" (id 1) (at 71.2471 106.9478 0)
(effects (font (size 1.27 1.27)) (justify left))
)
(property "Footprint" "TCY_solar:SM141K04LV" (id 2) (at 85.09 105.156 90)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "~" (id 3) (at 85.09 105.156 90)
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid ca2ccbf6-b2e5-4a9b-bc4d-684ed27bf55b))
(pin "2" (uuid e3b3ed30-1099-4d12-baa1-34038895f97e))
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(symbol (lib_id "power:GND") (at 114.3 100.33 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 048d78ec-a044-483f-b782-0942fd867e33) (uuid 3b8f2ef0-559a-4bbb-b1b1-a793b965aa19)
(property "Reference" "#PWR049" (id 0) (at 114.3 106.68 0) (property "Reference" "#PWR0149" (id 0) (at 85.09 115.57 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
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(property "Value" "GND" (id 1) (at 114.3 104.6544 0) (property "Value" "GND" (id 1) (at 85.09 113.5444 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
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(property "Footprint" "" (id 2) (at 114.3 100.33 0) (property "Footprint" "" (id 2) (at 85.09 109.22 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
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(property "Datasheet" "" (id 3) (at 114.3 100.33 0) (property "Datasheet" "" (id 3) (at 85.09 109.22 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(pin "1" (uuid 4f591fec-8771-4414-afc9-222c56939f82)) (pin "1" (uuid df9a530b-a451-4750-a2a9-ecdb9baf4a7b))
) )
(symbol (lib_id "power:GND") (at 99.06 100.33 0) (symbol (lib_id "power:GND") (at 99.06 100.33 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 23967b27-4826-44d0-861c-6940554d5463) (uuid 23967b27-4826-44d0-861c-6940554d5463)
(property "Reference" "#PWR048" (id 0) (at 99.06 106.68 0) (property "Reference" "#PWR0152" (id 0) (at 99.06 106.68 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Value" "GND" (id 1) (at 99.06 104.6544 0) (property "Value" "GND" (id 1) (at 99.06 104.6544 0)
@@ -388,46 +343,28 @@
(pin "1" (uuid 69933c30-96f3-4687-a9c3-129175464b17)) (pin "1" (uuid 69933c30-96f3-4687-a9c3-129175464b17))
) )
(symbol (lib_id "TCY_power_management:LM66100") (at 114.3 92.71 0) (symbol (lib_id "power:GND") (at 114.3 100.33 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 30946d46-6cd3-49a1-94ab-464d3efaadf4) (uuid 048d78ec-a044-483f-b782-0942fd867e33)
(property "Reference" "U5" (id 0) (at 114.3 84.1968 0)) (property "Reference" "#PWR0151" (id 0) (at 114.3 106.68 0)
(property "Value" "LM66100" (id 1) (at 114.3 86.4955 0))
(property "Footprint" "Package_TO_SOT_SMD:SOT-363_SC-70-6" (id 2) (at 114.3 110.49 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Datasheet" "https://www.ti.com/lit/ds/symlink/lm66100.pdf?ts=1611216893994&ref_url=https%253A%252F%252Fwww.google.com%252F" (id 3) (at 114.3 114.3 0) (property "Value" "GND" (id 1) (at 114.3 104.6544 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
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(pin "1" (uuid 21bc264f-1adc-4c29-87bb-ef8b761f4a60)) (property "Footprint" "" (id 2) (at 114.3 100.33 0)
(pin "2" (uuid 92fb66b3-6ee5-4a82-8100-735a257bf132))
(pin "3" (uuid 463a84e0-995a-4228-8d71-08eb9fc534af))
(pin "5" (uuid c6158a69-4803-4018-b7e3-682381779d8c))
(pin "6" (uuid 50a2a776-0876-4d9e-aac5-91da2605abb4))
)
(symbol (lib_id "power:GND") (at 85.09 129.54 0)
(in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 3b8f2ef0-559a-4bbb-b1b1-a793b965aa19)
(property "Reference" "#PWR047" (id 0) (at 85.09 135.89 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Value" "GND" (id 1) (at 85.09 133.8644 0) (property "Datasheet" "" (id 3) (at 114.3 100.33 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Footprint" "" (id 2) (at 85.09 129.54 0) (pin "1" (uuid 4f591fec-8771-4414-afc9-222c56939f82))
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "" (id 3) (at 85.09 129.54 0)
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid df9a530b-a451-4750-a2a9-ecdb9baf4a7b))
) )
(symbol (lib_id "power:GND") (at 124.46 100.33 0) (symbol (lib_id "power:GND") (at 124.46 100.33 0)
(in_bom yes) (on_board yes) (fields_autoplaced) (in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 855ea265-cf0f-467a-b7fb-994a04472f00) (uuid 855ea265-cf0f-467a-b7fb-994a04472f00)
(property "Reference" "#PWR050" (id 0) (at 124.46 106.68 0) (property "Reference" "#PWR0150" (id 0) (at 124.46 106.68 0)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
) )
(property "Value" "GND" (id 1) (at 124.46 104.6544 0) (property "Value" "GND" (id 1) (at 124.46 104.6544 0)
@@ -442,44 +379,6 @@
(pin "1" (uuid 3aa8aad3-b63f-46d8-a9a4-e8af144a499f)) (pin "1" (uuid 3aa8aad3-b63f-46d8-a9a4-e8af144a499f))
) )
(symbol (lib_id "Device:Solar_Cell") (at 85.09 116.84 0)
(in_bom yes) (on_board yes)
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(property "Reference" "SC7" (id 0) (at 75.0571 114.8091 0)
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(property "Value" "SM141K04L" (id 1) (at 71.2471 117.1078 0)
(effects (font (size 1.27 1.27)) (justify left))
)
(property "Footprint" "TCY_solar:SM141K04LV" (id 2) (at 85.09 115.316 90)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "~" (id 3) (at 85.09 115.316 90)
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid 1db5ee0a-1faa-4892-be81-e1af9e9280d7))
(pin "2" (uuid 8488e29d-c288-41ef-98a7-272be9ef7cc5))
)
(symbol (lib_id "Device:Solar_Cell") (at 85.09 127 0)
(in_bom yes) (on_board yes)
(uuid e7ba0631-8a32-4cf8-b1e0-7389be80c395)
(property "Reference" "SC8" (id 0) (at 75.0571 124.9691 0)
(effects (font (size 1.27 1.27)) (justify left))
)
(property "Value" "SM141K04L" (id 1) (at 71.2471 127.2678 0)
(effects (font (size 1.27 1.27)) (justify left))
)
(property "Footprint" "TCY_solar:SM141K04LV" (id 2) (at 85.09 125.476 90)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "~" (id 3) (at 85.09 125.476 90)
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid 76df5a64-5382-4fe2-83b7-16168e290617))
(pin "2" (uuid 2cd22269-6904-465f-b343-92420b748c73))
)
(symbol (lib_id "Device:C") (at 99.06 95.25 0) (symbol (lib_id "Device:C") (at 99.06 95.25 0)
(in_bom yes) (on_board yes) (in_bom yes) (on_board yes)
(uuid ee08ea61-0c8e-460a-9877-62d6a6cd5886) (uuid ee08ea61-0c8e-460a-9877-62d6a6cd5886)
@@ -502,13 +401,13 @@
(symbol (lib_id "Device:Solar_Cell") (at 85.09 96.52 0) (symbol (lib_id "Device:Solar_Cell") (at 85.09 96.52 0)
(in_bom yes) (on_board yes) (in_bom yes) (on_board yes)
(uuid f5a0f36c-e5f8-4dd9-8887-885f56ec2a71) (uuid f5a0f36c-e5f8-4dd9-8887-885f56ec2a71)
(property "Reference" "SC5" (id 0) (at 75.0571 94.4891 0) (property "Reference" "SC7" (id 0) (at 75.0571 94.4891 0)
(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
) )
(property "Value" "SM141K04L" (id 1) (at 71.2471 96.7878 0) (property "Value" "SM141K04L" (id 1) (at 71.2471 96.7878 0)
(effects (font (size 1.27 1.27)) (justify left)) (effects (font (size 1.27 1.27)) (justify left))
) )
(property "Footprint" "TCY_solar:SM141K04LV" (id 2) (at 85.09 94.996 90) (property "Footprint" "TCY_solar:SM141K04L" (id 2) (at 85.09 94.996 90)
(effects (font (size 1.27 1.27)) hide) (effects (font (size 1.27 1.27)) hide)
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(property "Datasheet" "~" (id 3) (at 85.09 94.996 90) (property "Datasheet" "~" (id 3) (at 85.09 94.996 90)
@@ -517,4 +416,41 @@
(pin "1" (uuid 3b156bda-6651-44cd-a108-773d3583d215)) (pin "1" (uuid 3b156bda-6651-44cd-a108-773d3583d215))
(pin "2" (uuid 4a941a7f-d1dd-482e-86bb-d6fbc2131969)) (pin "2" (uuid 4a941a7f-d1dd-482e-86bb-d6fbc2131969))
) )
(symbol (lib_id "Device:Solar_Cell") (at 85.09 106.68 0)
(in_bom yes) (on_board yes)
(uuid 0348ac21-372c-4d21-8b02-7758ba9a4bbd)
(property "Reference" "SC8" (id 0) (at 75.0571 104.6491 0)
(effects (font (size 1.27 1.27)) (justify left))
)
(property "Value" "SM141K04L" (id 1) (at 71.2471 106.9478 0)
(effects (font (size 1.27 1.27)) (justify left))
)
(property "Footprint" "TCY_solar:SM141K04L" (id 2) (at 85.09 105.156 90)
(effects (font (size 1.27 1.27)) hide)
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(property "Datasheet" "~" (id 3) (at 85.09 105.156 90)
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(pin "1" (uuid ca2ccbf6-b2e5-4a9b-bc4d-684ed27bf55b))
(pin "2" (uuid e3b3ed30-1099-4d12-baa1-34038895f97e))
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(symbol (lib_id "TCY_power_management:LM66100") (at 114.3 92.71 0)
(in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 30946d46-6cd3-49a1-94ab-464d3efaadf4)
(property "Reference" "U7" (id 0) (at 114.3 84.1968 0))
(property "Value" "LM66100" (id 1) (at 114.3 86.4955 0))
(property "Footprint" "Package_TO_SOT_SMD:SOT-363_SC-70-6" (id 2) (at 114.3 110.49 0)
(effects (font (size 1.27 1.27)) hide)
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(property "Datasheet" "https://www.ti.com/lit/ds/symlink/lm66100.pdf?ts=1611216893994&ref_url=https%253A%252F%252Fwww.google.com%252F" (id 3) (at 114.3 114.3 0)
(effects (font (size 1.27 1.27)) hide)
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(pin "1" (uuid 21bc264f-1adc-4c29-87bb-ef8b761f4a60))
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(pin "3" (uuid 463a84e0-995a-4228-8d71-08eb9fc534af))
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) )
File diff suppressed because it is too large Load Diff
-5
View File
@@ -1,5 +0,0 @@
Sun_sensor-backups/
gerbers/
bom/
replicate_layout.log
*.bak
File diff suppressed because it is too large Load Diff
File diff suppressed because it is too large Load Diff
File diff suppressed because it is too large Load Diff
File diff suppressed because it is too large Load Diff
File diff suppressed because it is too large Load Diff
File diff suppressed because it is too large Load Diff
File diff suppressed because it is too large Load Diff
@@ -1,18 +0,0 @@
(footprint "Alignment_hole" (version 20211014) (generator pcbnew)
(layer "F.Cu")
(tedit 0)
(attr through_hole exclude_from_pos_files exclude_from_bom)
(fp_text reference "REF**" (at 0 -2 unlocked) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp fa4317a5-84bf-4bc5-a76e-39c9dc74322a)
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(fp_text value "Alignment_hole" (at 0 3.5 unlocked) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 5c6e8499-7ddb-488e-b28a-698103ce6e3c)
)
(fp_text user "${REFERENCE}" (at 0 5 unlocked) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 15e51ca5-9eb7-44d4-880d-ebea60015cd4)
)
(pad "" thru_hole circle (at 0 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask) (tstamp b1f6e753-2943-4966-9a1d-84d501867e27))
)
@@ -1,71 +0,0 @@
(footprint "Sun_shiled_stencil" (version 20211014) (generator pcbnew)
(layer "F.Cu")
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(fp_text reference "REF**" (at 0 -7 unlocked) (layer "F.SilkS")
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(fp_text value "Sun_shiled_stencil" (at 0 6.25 unlocked) (layer "F.Fab")
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(fp_text user "${REFERENCE}" (at 0 7.75 unlocked) (layer "F.Fab")
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(fp_lib_table
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build/
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-19
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@@ -1,19 +0,0 @@
{
"version": "0.2.0",
"configurations": [
{
"type": "cortex-debug",
"request": "launch",
"servertype": "openocd",
"cwd": "${workspaceRoot}",
"executable": "${workspaceRoot}/build/Sun_sensor.elf",
"name": "GDB + OpenOCD",
"device": "STM32L432",
"configFiles": [
"interface/stlink.cfg",
"target/stm32l4x.cfg"
]
}
]
}
@@ -1,894 +0,0 @@
/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V5.1.0
* @date 08. May 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* CMSIS compiler control DSP macros */
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __ARM_FEATURE_DSP 1
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __memory_changed()
#endif
/* ######################### Startup and Lowlevel Init ######################## */
#ifndef __PROGRAM_START
#define __PROGRAM_START __main
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __Vectors
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return result;
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */
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File diff suppressed because it is too large Load Diff
@@ -1,283 +0,0 @@
/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.1.0
* @date 09. October 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */
File diff suppressed because it is too large Load Diff
@@ -1,964 +0,0 @@
/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.1.0
* @date 08. May 2019
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2019 IAR Systems
// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
/* Macros already defined */
#else
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
#if __ARM_ARCH == 6
#define __ARM_ARCH_6M__ 1
#elif __ARM_ARCH == 7
#if __ARM_FEATURE_DSP
#define __ARM_ARCH_7EM__ 1
#else
#define __ARM_ARCH_7M__ 1
#endif
#endif /* __ARM_ARCH */
#endif /* __ARM_ARCH_PROFILE == 'M' */
#endif
/* Alternativ core deduction for older ICCARM's */
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
#define __ARM_ARCH_6M__ 1
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
#define __ARM_ARCH_7M__ 1
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
#define __ARM_ARCH_7EM__ 1
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#else
#error "Unknown target."
#endif
#endif
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
#define __IAR_M0_FAMILY 1
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
#define __IAR_M0_FAMILY 1
#else
#define __IAR_M0_FAMILY 0
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#if __ICCARM_V8
#define __RESTRICT __restrict
#else
/* Needs IAR language extensions */
#define __RESTRICT restrict
#endif
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __PROGRAM_START
#define __PROGRAM_START __iar_program_start
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP CSTACK$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT CSTACK$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __vector_table
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#else
#define __get_FPSCR() ( 0 )
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#define __get_IPSR() (__arm_rsr("IPSR"))
#define __get_MSP() (__arm_rsr("MSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __get_MSPLIM() (0U)
#else
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
#endif
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
#define __get_PSP() (__arm_rsr("PSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __get_PSPLIM() (0U)
#else
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
#endif
#define __get_xPSR() (__arm_rsr("xPSR"))
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __set_MSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
#endif
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __set_PSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
#else
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#endif
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#if !__IAR_M0_FAMILY
#define __SSAT __iar_builtin_SSAT
#endif
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#if !__IAR_M0_FAMILY
#define __USAT __iar_builtin_USAT
#endif
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#if __ARM_MEDIA__
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#endif
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#define __CLZ __cmsis_iar_clz_not_active
#define __SSAT __cmsis_iar_ssat_not_active
#define __USAT __cmsis_iar_usat_not_active
#define __RBIT __cmsis_iar_rbit_not_active
#define __get_APSR __cmsis_iar_get_APSR_not_active
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#undef __CLZ
#undef __SSAT
#undef __USAT
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
if (data == 0U) { return 32U; }
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
r <<= 1U;
r |= v & 1U;
sc--;
}
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t res;
__asm("MRS %0,APSR" : "=r" (res));
return res;
}
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#undef __get_FPSCR
#undef __set_FPSCR
#define __get_FPSCR() (0)
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __NOP __no_operation
#define __get_xPSR __get_PSR
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
#endif
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
return(result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint32_t __get_MSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__asm volatile("MSR SP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
#endif
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t res;
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t res;
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t res;
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#undef __IAR_FT
#undef __IAR_M0_FAMILY
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#endif /* __CMSIS_ICCARM_H__ */
@@ -1,39 +0,0 @@
/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.3
* @date 24. June 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif
File diff suppressed because it is too large Load Diff
File diff suppressed because it is too large Load Diff
File diff suppressed because it is too large Load Diff
@@ -1,952 +0,0 @@
/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V5.0.6
* @date 13. March 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
#include "cmsis_version.h"
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (0U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RESERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t vectors = 0x0U;
(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
/* ARM Application Note 321 states that the M0 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t vectors = 0x0U;
return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
File diff suppressed because it is too large Load Diff
@@ -1,979 +0,0 @@
/**************************************************************************//**
* @file core_cm1.h
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
* @version V1.0.1
* @date 12. November 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM1_H_GENERIC
#define __CORE_CM1_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M1
@{
*/
#include "cmsis_version.h"
/* CMSIS CM1 definitions */
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (1U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM1_H_DEPENDANT
#define __CORE_CM1_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM1_REV
#define __CM1_REV 0x0100U
#warning "__CM1_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M1 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M1 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
/* ARM Application Note 321 states that the M1 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
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@@ -1,272 +0,0 @@
/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.1.0
* @date 08. March 2019
******************************************************************************/
/*
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
(((MPU_RASR_ENABLE_Msk))))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if shareable) or 010b (if non-shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif
@@ -1,346 +0,0 @@
/******************************************************************************
* @file mpu_armv8.h
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
* @version V5.1.0
* @date 08. March 2019
******************************************************************************/
/*
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV8_H
#define ARM_MPU_ARMV8_H
/** \brief Attribute for device memory (outer only) */
#define ARM_MPU_ATTR_DEVICE ( 0U )
/** \brief Attribute for non-cacheable, normal memory */
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
/** \brief Attribute for normal memory (outer and inner)
* \param NT Non-Transient: Set to 1 for non-transient data.
* \param WB Write-Back: Set to 1 to use write-back update policy.
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
*/
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
/** \brief Memory Attribute
* \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
/** \brief Normal memory non-shareable */
#define ARM_MPU_SH_NON (0U)
/** \brief Normal memory outer shareable */
#define ARM_MPU_SH_OUTER (2U)
/** \brief Normal memory inner shareable */
#define ARM_MPU_SH_INNER (3U)
/** \brief Memory access permissions
* \param RO Read-Only: Set to 1 for read-only memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
*/
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
/** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
* \param SH Defines the Shareability domain for this memory region.
* \param RO Read-Only: Set to 1 for a read-only memory region.
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
*/
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
((BASE & MPU_RBAR_BASE_Msk) | \
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
/** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR(LIMIT, IDX) \
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#if defined(MPU_RLAR_PXN_Pos)
/** \brief Region Limit Address Register with PXN value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#endif
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#ifdef MPU_NS
/** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the Non-secure MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#endif
/** Set the memory attribute encoding to the given MPU.
* \param mpu Pointer to the MPU to be configured.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
{
const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos;
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
return; // invalid index
}
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
}
/** Set the memory attribute encoding.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
}
#ifdef MPU_NS
/** Set the memory attribute encoding to the Non-secure MPU.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
}
#endif
/** Clear and disable the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
mpu->RNR = rnr;
mpu->RLAR = 0U;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU, rnr);
}
#ifdef MPU_NS
/** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
}
#endif
/** Configure the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
mpu->RNR = rnr;
mpu->RBAR = rbar;
mpu->RLAR = rlar;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
}
#ifdef MPU_NS
/** Configure the given Non-secure MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
}
#endif
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table to the given MPU.
* \param mpu Pointer to the MPU registers to be used.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U) {
mpu->RNR = rnr;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
} else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
table += c;
cnt -= c;
rnrOffset = 0U;
rnrBase += MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
}
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
}
}
/** Load the given number of MPU regions from a table.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
}
#ifdef MPU_NS
/** Load the given number of MPU regions from a table to the Non-secure MPU.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
}
#endif
#endif
@@ -1,70 +0,0 @@
/******************************************************************************
* @file tz_context.h
* @brief Context Management for Armv8-M TrustZone
* @version V1.0.1
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef TZ_CONTEXT_H
#define TZ_CONTEXT_H
#include <stdint.h>
#ifndef TZ_MODULEID_T
#define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process.
typedef uint32_t TZ_ModuleId_t;
#endif
/// \details TZ Memory ID identifies an allocated memory slot.
typedef uint32_t TZ_MemoryId_t;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
uint32_t TZ_InitContextSystem_S (void);
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
#endif // TZ_CONTEXT_H
@@ -1,58 +0,0 @@
/******************************************************************************
* @file main_s.c
* @brief Code template for secure main function
* @version V1.1.1
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* Use CMSE intrinsics */
#include <arm_cmse.h>
#include "RTE_Components.h"
#include CMSIS_device_header
/* TZ_START_NS: Start address of non-secure application */
#ifndef TZ_START_NS
#define TZ_START_NS (0x200000U)
#endif
/* typedef for non-secure callback functions */
typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call));
/* Secure main() */
int main(void) {
funcptr_void NonSecure_ResetHandler;
/* Add user setup code for secure part here*/
/* Set non-secure main stack (MSP_NS) */
__TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS)));
/* Get non-secure reset handler */
NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U)));
/* Start non-secure state software application */
NonSecure_ResetHandler();
/* Non-secure software does not return, this code is not executed */
while (1) {
__NOP();
}
}
@@ -1,200 +0,0 @@
/******************************************************************************
* @file tz_context.c
* @brief Context Management for Armv8-M TrustZone - Sample implementation
* @version V1.1.1
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2016-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "RTE_Components.h"
#include CMSIS_device_header
#include "tz_context.h"
/// Number of process slots (threads may call secure library code)
#ifndef TZ_PROCESS_STACK_SLOTS
#define TZ_PROCESS_STACK_SLOTS 8U
#endif
/// Stack size of the secure library code
#ifndef TZ_PROCESS_STACK_SIZE
#define TZ_PROCESS_STACK_SIZE 256U
#endif
typedef struct {
uint32_t sp_top; // stack space top
uint32_t sp_limit; // stack space limit
uint32_t sp; // current stack pointer
} stack_info_t;
static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS];
static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U];
static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
__attribute__((cmse_nonsecure_entry))
uint32_t TZ_InitContextSystem_S (void) {
uint32_t n;
if (__get_IPSR() == 0U) {
return 0U; // Thread Mode
}
for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) {
ProcessStackInfo[n].sp = 0U;
ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n];
ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE;
*((uint32_t *)ProcessStackMemory[n]) = n + 1U;
}
*((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU;
ProcessStackFreeSlot = 0U;
// Default process stack pointer and stack limit
__set_PSPLIM((uint32_t)ProcessStackMemory);
__set_PSP ((uint32_t)ProcessStackMemory);
// Privileged Thread Mode using PSP
__set_CONTROL(0x02U);
return 1U; // Success
}
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
__attribute__((cmse_nonsecure_entry))
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) {
uint32_t slot;
(void)module; // Ignore (fixed Stack size)
if (__get_IPSR() == 0U) {
return 0U; // Thread Mode
}
if (ProcessStackFreeSlot == 0xFFFFFFFFU) {
return 0U; // No slot available
}
slot = ProcessStackFreeSlot;
ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]);
ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top;
return (slot + 1U);
}
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
__attribute__((cmse_nonsecure_entry))
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) {
uint32_t slot;
if (__get_IPSR() == 0U) {
return 0U; // Thread Mode
}
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
return 0U; // Invalid ID
}
slot = id - 1U;
if (ProcessStackInfo[slot].sp == 0U) {
return 0U; // Inactive slot
}
ProcessStackInfo[slot].sp = 0U;
*((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot;
ProcessStackFreeSlot = slot;
return 1U; // Success
}
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
__attribute__((cmse_nonsecure_entry))
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) {
uint32_t slot;
if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
return 0U; // Thread Mode or using Main Stack for threads
}
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
return 0U; // Invalid ID
}
slot = id - 1U;
if (ProcessStackInfo[slot].sp == 0U) {
return 0U; // Inactive slot
}
// Setup process stack pointer and stack limit
__set_PSPLIM(ProcessStackInfo[slot].sp_limit);
__set_PSP (ProcessStackInfo[slot].sp);
return 1U; // Success
}
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
__attribute__((cmse_nonsecure_entry))
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) {
uint32_t slot;
uint32_t sp;
if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
return 0U; // Thread Mode or using Main Stack for threads
}
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
return 0U; // Invalid ID
}
slot = id - 1U;
if (ProcessStackInfo[slot].sp == 0U) {
return 0U; // Inactive slot
}
sp = __get_PSP();
if ((sp < ProcessStackInfo[slot].sp_limit) ||
(sp > ProcessStackInfo[slot].sp_top)) {
return 0U; // SP out of range
}
ProcessStackInfo[slot].sp = sp;
// Default process stack pointer and stack limit
__set_PSPLIM((uint32_t)ProcessStackMemory);
__set_PSP ((uint32_t)ProcessStackMemory);
return 1U; // Success
}
@@ -1,136 +0,0 @@
cmake_minimum_required (VERSION 3.6)
cmake_policy(SET CMP0077 NEW)
# The tests are assuming that MATRIX_CHECK is enabled when building
# CMSIS-DSP.
set(MATRIXCHECK ON)
set(FASTMATHCOMPUTATIONS OFF)
option(DUMPPATTERN "Dump test patterns when test is failing" ON)
option(CUSTOMIZE_TESTS "Enable customizations of tests" ON)
option(BASICMATH_TESTS "Enable Basic Math testing" ON)
option(COMPLEXMATH_TESTS "Enable Complex Math testing" ON)
option(CONTROLLER_TESTS "Enable Controller testing" ON)
option(FASTMATH_TESTS "Enable Fast Math testing" ON)
option(INTRINSICS_TESTS "Enable Intrinsics testing" ON)
option(FILTERING_TESTS "Enable Filtering testing" ON)
option(MATRIX_TESTS "Enable Matrix testing" ON)
option(STATISTICS_TESTS "Enable Statistics testing" ON)
option(SUPPORT_TESTS "Enable Support testing" ON)
option(TRANSFORM_TESTS "Enable Transform testing" ON)
project(DSP_Lib_TestSuite)
# Needed to find the config modules
list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/..)
set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../..)
file(GLOB MAIN "Common/src/*.c")
file(GLOB BASICMATH_TESTS_SRC "Common/src/basic_math_tests/*.c")
file(GLOB COMPLEXMATH_TESTS_SRC "Common/src/complex_math_tests/*.c")
file(GLOB CONTROLLER_TESTS_SRC "Common/src/controller_tests/*.c")
file(GLOB FASTMATH_TESTS_SRC "Common/src/fast_math_tests/*.c")
file(GLOB FILTERING_TESTS_SRC "Common/src/filtering_tests/*.c")
file(GLOB INTRINSINCS_TESTS_SRC "Common/src/intrinsics_tests/*.c")
file(GLOB MATRIX_TESTS_SRC "Common/src/matrix_tests/*.c")
file(GLOB STATISTICS_TESTS_SRC "Common/src/statistics_tests/*.c")
file(GLOB SUPPORT_TESTS_SRC "Common/src/support_tests/*.c")
file(GLOB TRANSFORM_TESTS_SRC "Common/src/transform_tests/*.c")
file(GLOB JTEST_MAIN "Common/JTest/src/*.c")
set(TESTSRC ${MAIN}
${BASICMATH_TESTS_SRC}
${COMPLEXMATH_TESTS_SRC}
${CONTROLLER_TESTS_SRC}
${FASTMATH_TESTS_SRC}
${FILTERING_TESTS_SRC}
${INTRINSINCS_TESTS_SRC}
${MATRIX_TESTS_SRC}
${STATISTICS_TESTS_SRC}
${SUPPORT_TESTS_SRC}
${TRANSFORM_TESTS_SRC}
${JTEST_MAIN}
)
set(JINCS
Common/JTest/inc
Common/JTest/inc/arr_desc
Common/inc/basic_math_tests
Common/inc/complex_math_tests
Common/inc/controller_tests
Common/inc/fast_math_tests
Common/inc/filtering_tests
Common/inc/intrinsics_tests
Common/inc/matrix_tests
Common/inc/statistics_tests
Common/inc/support_tests
Common/inc/transform_tests
)
add_subdirectory(../Source bin_dsp)
add_subdirectory(RefLibs bin_ref)
add_executable(DSP_Lib_TestSuite)
if (CUSTOMIZE_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE CUSTOMIZE_TESTS)
endif()
if (BASICMATH_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_BASICMATH_TESTS)
endif()
if (COMPLEXMATH_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_COMPLEXMATH_TESTS)
endif()
if (CONTROLLER_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_CONTROLLER_TESTS)
endif()
if (FASTMATH_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_FASTMATH_TESTS)
endif()
if (FILTERING_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_FILTERING_TESTS)
endif()
if (INTRINSICS_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_INTRINSICS_TESTS)
endif()
if (MATRIX_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_MATRIX_TESTS)
endif()
if (STATISTICS_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_STATISTICS_TESTS)
endif()
if (SUPPORT_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_SUPPORT_TESTS)
endif()
if (TRANSFORM_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_TRANSFORM_TESTS)
endif()
if (DUMPPATTERN)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE DUMPPATTERN)
endif()
# Change behavior of configBoot for scatter file
set(TESTFRAMEWORK ON)
include(configBoot)
file(COPY ${ROOT}/CMSIS/DSP/Examples/ARM/boot/RTE_Components.h DESTINATION tempLink)
target_link_libraries(DSP_Lib_TestSuite PRIVATE CMSISDSP)
target_link_libraries(DSP_Lib_TestSuite PRIVATE DspRefLibs)
target_sources(DSP_Lib_TestSuite PRIVATE ${TESTSRC})
### Includes
target_include_directories(DSP_Lib_TestSuite PRIVATE "Common/inc")
target_include_directories(DSP_Lib_TestSuite PRIVATE "Common/inc/templates")
target_include_directories(DSP_Lib_TestSuite PRIVATE ${JINCS})
@@ -1,220 +0,0 @@
#ifndef _ARR_DESC_H_
#define _ARR_DESC_H_
/*--------------------------------------------------------------------------------*/
/* Includes */
/*--------------------------------------------------------------------------------*/
#include <stdint.h>
#include <string.h> /* memset() */
#include "../util/util.h" /* CONCAT() */
/*--------------------------------------------------------------------------------*/
/* Type Definitions */
/*--------------------------------------------------------------------------------*/
/**
* Array-descriptor struct.
*/
typedef struct ARR_DESC_struct
{
void * data_ptr; /* Pointer to the array contents. */
int32_t element_count; /* Number of current elements. */
int32_t element_size; /* Size of current elements in bytes. */
int32_t underlying_size; /* Size of underlying array in bytes. */
} ARR_DESC_t;
/*--------------------------------------------------------------------------------*/
/* Macros and Defines */
/*--------------------------------------------------------------------------------*/
/**
* Prefix of the array variable's name when creating an array and an array
* descriptor at the same time.
*/
#define ARR_DESC_ARR_PREFIX ARR_DESC_ARR_
/**
* Evaluate to the array variable's name when creating an array and an array
* descriptor at the same time.
*/
#define ARR_DESC_ARR_NAME(name) \
CONCAT(ARR_DESC_ARR_PREFIX, name)
/**
* Define an #ARR_DESC_t by itself.
*
* @note The user must supply an array to store the data used by the
* #ARR_DESC_t.
*/
#define ARR_DESC_INTERNAL_DEFINE(name, data_ptr, \
element_count, element_size) \
ARR_DESC_t name = { \
data_ptr, \
element_count, \
element_size, \
element_count * element_size \
} \
/**
* Define both an array and an #ARR_DESC_t that describes it.
*
* @note Use the #CURLY() macro for the content field; it provides the curly
* braces necessary for an array initialization.
*/
#define ARR_DESC_DEFINE(type, name, element_count, content) \
type ARR_DESC_ARR_NAME(name)[element_count] = content; \
ARR_DESC_INTERNAL_DEFINE(name, \
&ARR_DESC_ARR_NAME(name), \
element_count, \
sizeof(type)) /* Note the lacking semicolon */
/**
* Create a #ARR_DESC_t which refers to a subset of the data in another.
*
* The new #ARR_DESC_t shares the same underlying array as the aliased
* #ARR_DESC_t, but only describes a subset of the originals values.
*/
#define ARR_DESC_DEFINE_SUBSET(name, original, element_cnt) \
ARR_DESC_INTERNAL_DEFINE(name, \
&ARR_DESC_ARR_NAME(original), \
element_cnt, \
sizeof(ARR_DESC_ARR_NAME(original)[0]) \
) /* Note the lacking semicolon */
/**
* Creat an #ARR_DESC_t which points to the data in an existing array.
*
* @param start_idx Offset in array_ptr of first element.
* @param element_cnt Number of elements to include in the #ARR_DESC_t.
*
* @example
*
* float my_floats[4] = {0.0f, 1.0f, 2.0f, 3.0f};
*
* ARR_DESC_DEFINE_USING_ARR(my_arr_desc, my_floats, 1, 3);
*
* printf("Element 0: %f\n", ARR_DESC_ELT(float, 0, &my_arr_desc));
* printf("Element 1: %f\n", ARR_DESC_ELT(float, 1, &my_arr_desc));
*
* Outputs:
*
* Element 0: 1.000000
* Element 1: 2.000000
*
* @warning There are no checks in place to catch invalid start indices; This
* is left to the user.
*/
#define ARR_DESC_DEFINE_USING_ARR(type, name, array_ptr, start_idx, element_cnt) \
ARR_DESC_INTERNAL_DEFINE( \
name, \
(type *) (array_ptr + start_idx), \
element_cnt, \
sizeof(type) \
) /* Note the lacking semicolon*/
/**
* Declare an #ARR_DESC_t object.
*/
#define ARR_DESC_DECLARE(name) \
extern ARR_DESC_t name /* Note the lacking semicolon */
/**
* Evaluate to the number of bytes stored in the #ARR_DESC_t.
*/
#define ARR_DESC_BYTES(arr_desc_ptr) \
((arr_desc_ptr)->element_count * (arr_desc_ptr)->element_size)
/**
* Set the contents of #ARR_DESC_t to value.
*/
#define ARR_DESC_MEMSET(arr_desc_ptr, value, bytes) \
do \
{ \
memset((arr_desc_ptr)->data_ptr, \
value, \
BOUND(0, \
(arr_desc_ptr)->underlying_size, \
bytes) \
); \
} while (0)
/**
* Perform a memcpy of 'bytes' bytes from the source #ARR_DESC_t to the
* destination #ARR_DESC_t.
*/
#define ARR_DESC_MEMCPY(arr_desc_dest_ptr, arr_desc_src_ptr, bytes) \
do \
{ \
memcpy((arr_desc_dest_ptr)->data_ptr, \
(arr_desc_src_ptr)->data_ptr, \
BOUND(0, \
(arr_desc_dest_ptr)->underlying_size, \
bytes)); \
} while (0)
/**
* Evaluate to true if the source #ARR_DESC_t contents will fit into the
* destination #ARR_DESC_t and false otherwise.
*/
#define ARR_DESC_COPYABLE(arr_desc_dest_ptr, arr_desc_src_ptr) \
(ARR_DESC_BYTES(arr_desc_src_ptr) <= \
(arr_desc_dest_ptr)->underlying_size)
/**
* Copy all the data from the source #ARR_DESC_t to the destination
* #ARR_DESC_t.
*
* @note If the destination #ARR_DESC_t is too small to fit the source data the
* copy is aborted and nothing happens.
*/
#define ARR_DESC_COPY(arr_desc_dest_ptr, arr_desc_src_ptr) \
do \
{ \
if (ARR_DESC_COPYABLE(arr_desc_dest_ptr, \
arr_desc_src_ptr)) \
{ \
ARR_DESC_MEMCPY(arr_desc_dest_ptr, \
arr_desc_src_ptr, \
ARR_DESC_BYTES(arr_desc_src_ptr)); \
/* Update the properties*/ \
(arr_desc_dest_ptr)->element_count = \
(arr_desc_src_ptr)->element_count; \
(arr_desc_dest_ptr)->element_size = \
(arr_desc_src_ptr)->element_size; \
} \
} while (0)
/**
* Compare the data in two #ARR_DESC_t structs for the specified number of
* bytes.
*/
#define ARR_DESC_MEMCMP(arr_desc_ptr_a, arr_desc_ptr_b, bytes) \
memcmp((arr_desc_ptr_a)->data_ptr, \
(arr_desc_ptr_b)->data_ptr, \
bytes) /* Note the lacking semicolon */ \
/**
* Zero out the contents of the #ARR_DESC_t.
*/
#define ARR_DESC_ZERO(arr_desc_ptr) \
ARR_DESC_MEMSET(arr_desc_ptr, \
0, \
(arr_desc_ptr)->underlying_size)
/**
* Evaluate to the data address in #ARR_DESC_t at offset.
*/
#define ARR_DESC_DATA_ADDR(type, arr_desc_ptr, offset) \
((void*)(((type *) \
((arr_desc_ptr)->data_ptr)) \
+ offset))
/**
* Evaluate to the element in #ARR_DESC_t with type at idx.
*/
#define ARR_DESC_ELT(type, idx, arr_desc_ptr) \
(*((type *) ARR_DESC_DATA_ADDR(type, \
arr_desc_ptr, \
idx)))
#endif /* _ARR_DESC_H_ */
@@ -1,17 +0,0 @@
#ifndef _JTEST_H_
#define _JTEST_H_
/*--------------------------------------------------------------------------------*/
/* Includes */
/*--------------------------------------------------------------------------------*/
#include "jtest_fw.h"
#include "jtest_test.h"
#include "jtest_test_define.h"
#include "jtest_test_call.h"
#include "jtest_group.h"
#include "jtest_group_define.h"
#include "jtest_group_call.h"
#include "jtest_cycle.h"
#endif /* _JTEST_H_ */
@@ -1,79 +0,0 @@
#ifndef _JTEST_CYCLE_H_
#define _JTEST_CYCLE_H_
/*--------------------------------------------------------------------------------*/
/* Includes */
/*--------------------------------------------------------------------------------*/
#include "jtest_fw.h" /* JTEST_DUMP_STRF() */
#include "jtest_systick.h"
#include "jtest_util.h" /* STR() */
/*--------------------------------------------------------------------------------*/
/* Declare Module Variables */
/*--------------------------------------------------------------------------------*/
extern const char * JTEST_CYCLE_STRF;
/*--------------------------------------------------------------------------------*/
/* Macros and Defines */
/*--------------------------------------------------------------------------------*/
/**
* Wrap the function call, fn_call, to count execution cycles and display the
* results.
*/
/* skipp function name + param
#define JTEST_COUNT_CYCLES(fn_call) \
do \
{ \
uint32_t __jtest_cycle_end_count; \
\
JTEST_SYSTICK_RESET(SysTick); \
JTEST_SYSTICK_START(SysTick); \
\
fn_call; \
\
__jtest_cycle_end_count = \
JTEST_SYSTICK_VALUE(SysTick); \
\
JTEST_SYSTICK_RESET(SysTick); \
JTEST_DUMP_STRF(JTEST_CYCLE_STRF, \
STR(fn_call), \
(JTEST_SYSTICK_INITIAL_VALUE - \
__jtest_cycle_end_count)); \
} while (0)
*/
#ifndef ARMv7A
#define JTEST_COUNT_CYCLES(fn_call) \
do \
{ \
uint32_t __jtest_cycle_end_count; \
\
JTEST_SYSTICK_RESET(SysTick); \
JTEST_SYSTICK_START(SysTick); \
\
fn_call; \
\
__jtest_cycle_end_count = \
JTEST_SYSTICK_VALUE(SysTick); \
\
JTEST_SYSTICK_RESET(SysTick); \
JTEST_DUMP_STRF(JTEST_CYCLE_STRF, \
(JTEST_SYSTICK_INITIAL_VALUE - \
__jtest_cycle_end_count)); \
} while (0)
#else
/* TODO */
#define JTEST_COUNT_CYCLES(fn_call) \
do \
{ \
fn_call; \
} while (0)
#endif
#endif /* _JTEST_CYCLE_H_ */
@@ -1,37 +0,0 @@
#ifndef _JTEST_DEFINE_H_
#define _JTEST_DEFINE_H_
/*--------------------------------------------------------------------------------*/
/* Macros and Defines */
/*--------------------------------------------------------------------------------*/
/**
* Makes a symbol for use as a struct name. Names made this way have two parts;
* the first parts is a prefix common to all structs of that class. The second
* is a specifier which differs for each instance of that struct type.
*/
#define JTEST_STRUCT_NAME(prefix, specifier) \
CONCAT(prefix, specifier)
/**
* Define a struct with type with a name generated by #JTEST_STRUCT_NAME().
*/
#define JTEST_DEFINE_STRUCT(type, struct_name) \
type struct_name
/**
* Declare a struct with type with a name generated by #JTEST_STRUCT_NAME().
*/
#define JTEST_DECLARE_STRUCT(struct_definition) \
extern struct_definition
/**
* Define and initialize a struct (created with JTEST_DEFINE_STRUCT()) and
* initialize it with init_values.
*/
#define JTEST_INIT_STRUCT(struct_definition, init_values) \
struct_definition = { \
init_values \
}
#endif /* _JTEST_DEFINE_H_ */
@@ -1,282 +0,0 @@
#ifndef _JTEST_FW_H_
#define _JTEST_FW_H_
/*--------------------------------------------------------------------------------*/
/* Includes */
/*--------------------------------------------------------------------------------*/
#include <stdint.h> /* int32_t */
#include <string.h> /* strcpy() */
#include <stdio.h> /* sprintf() */
#include "jtest_pf.h" /* Extend JTEST_FW_t with Pass/Fail data */
#include "jtest_group.h"
/*--------------------------------------------------------------------------------*/
/* Type Definitions */
/*--------------------------------------------------------------------------------*/
/**
* A struct used to interface with the Keil Debugger.
*/
typedef struct JTEST_FW_struct
{
/* Action Triggers: The Keil debugger monitors these values for changes. In
* response to a change, the debugger executes code on the host. */
volatile int32_t test_start;
volatile int32_t test_end;
volatile int32_t group_start;
volatile int32_t group_end;
volatile int32_t dump_str;
volatile int32_t dump_data;
volatile int32_t exit_fw;
JTEST_GROUP_t * current_group_ptr;
/* Buffers: The C-code cannot send strings and data directly to the
* debugging framework. Instead, the debugger can be told to read 128 byte
* (by default) chunks of memory. Data received in this manner requires
* post-processing to be legible.*/
char * str_buffer;
char * data_buffer;
/* Pass/Fail Data */
JTEST_PF_MEMBERS;
} JTEST_FW_t;
/*--------------------------------------------------------------------------------*/
/* Macros and Defines */
/*--------------------------------------------------------------------------------*/
/**
* Default name for the JTEST_FW struct.
*
* Define your own if you want the variable containing the #JTEST_FW_t to have
* a different name.
*/
#ifndef JTEST_FW
#define JTEST_FW JTEST_FW
#endif
/**
* Default name for the JTEST_FW_STR_BUFFER.
*
* Define your own if you want the variable containing the char buffer to have
* a different name.
*/
#ifndef JTEST_FW_STR_BUFFER
#define JTEST_FW_STR_BUFFER JTEST_FW_STR_BUFFER
#endif
/**
* Size of the #JTEST_FW_t, output string-buffer.
*
* If you change this value, make sure the "dump_str_fn" and "dump_data_fn"
* functions in jtest_fns.ini uses the same size. If you aren't sure, read the
* documentation Keil Debugger Command 'DISPLAY'.
*/
#define JTEST_BUF_SIZE 256
/**
* The maximum number of bytes output at once using #JTEST_DUMP_STRF().
*/
#define JTEST_STR_MAX_OUTPUT_SIZE 128
/**
* The maximum number of block transimissions needed to send a string from a
* buffer with JTEST_BUF_SIZE.
*/
#define JTEST_STR_MAX_OUTPUT_SEGMENTS \
(JTEST_BUF_SIZE / JTEST_STR_MAX_OUTPUT_SIZE)
/**
* Initialize the JTEST framework.
*/
#define JTEST_INIT() \
do \
{ \
JTEST_FW.str_buffer = JTEST_FW_STR_BUFFER; \
} while (0)
/* Debugger Action-triggering Macros */
/*--------------------------------------------------------------------------------*/
/**
* Dispatch macro to trigger various actions in the Keil Debugger.
*/
#define JTEST_TRIGGER_ACTION(action_name) \
do \
{ \
action_name(); \
} while (0)
/**
* Trigger the "Test Start" action in the Keil Debugger.
*/
#define JTEST_ACT_TEST_START() \
JTEST_TRIGGER_ACTION(test_start)
/**
* Trigger the "Test End" action in the Keil Debugger.
*/
#define JTEST_ACT_TEST_END() \
JTEST_TRIGGER_ACTION(test_end)
/**
* Trigger the "Group Start" action in the Keil Debugger.
*/
#define JTEST_ACT_GROUP_START() \
JTEST_TRIGGER_ACTION(group_start)
/**
* Trigger the "Group End" action in the Keil Debugger.
*/
#define JTEST_ACT_GROUP_END() \
JTEST_TRIGGER_ACTION(group_end)
/**
* Fill the buffer named buf_name with value and dump it to the Keil debugger
* using action.
*/
#if defined(ARMv7A) || defined(FILEIO)
#define JTEST_ACT_DUMP(action, buf_name, value) \
do \
{ \
JTEST_CLEAR_BUFFER(buf_name); \
printf("%s",value); \
strcpy(JTEST_FW.buf_name, (value)); \
JTEST_TRIGGER_ACTION(action); \
} while (0)
#else
#define JTEST_ACT_DUMP(action, buf_name, value) \
do \
{ \
JTEST_CLEAR_BUFFER(buf_name); \
strcpy(JTEST_FW.buf_name, (value)); \
JTEST_TRIGGER_ACTION(action); \
} while (0)
#endif
/**
* Trigger the "Exit Framework" action in the Keil Debugger.
*/
#define JTEST_ACT_EXIT_FW() \
do \
{ \
JTEST_TRIGGER_ACTION(exit_fw); \
} while (0)
/* Buffer Manipulation Macros */
/*--------------------------------------------------------------------------------*/
/**
* Clear the JTEST_FW buffer with name buf_name.
*/
#define JTEST_CLEAR_BUFFER(buf_name) \
do \
{ \
memset(JTEST_FW.buf_name, 0, JTEST_BUF_SIZE); \
} while (0)
/**
* Clear the memory needed for the JTEST_FW's string buffer.
*/
#define JTEST_CLEAR_STR_BUFFER() \
JTEST_CLEAR_BUFFER(str_buffer)
/**
* Clear the memory needed for the JTEST_FW's data buffer.
*/
#define JTEST_CLEAR_DATA_BUFFER() \
JTEST_CLEAR_BUFFER(data_buffer)
/**
* Dump the given string to the Keil Debugger.
*/
#define JTEST_DUMP_STR(string) \
JTEST_ACT_DUMP(dump_str, str_buffer, string)
/**
* Dump a formatted string to the Keil Debugger.
*/
#if defined(ARMv7A) || defined(FILEIO)
#define JTEST_DUMP_STRF(format_str, ... ) \
do \
{ \
JTEST_CLEAR_STR_BUFFER(); \
sprintf(JTEST_FW.str_buffer,format_str, __VA_ARGS__); \
printf("%s",JTEST_FW.str_buffer); \
jtest_dump_str_segments(); \
} while (0)
#else
#define JTEST_DUMP_STRF(format_str, ... ) \
do \
{ \
JTEST_CLEAR_STR_BUFFER(); \
sprintf(JTEST_FW.str_buffer,format_str, __VA_ARGS__); \
jtest_dump_str_segments(); \
} while (0)
#endif
/* Pass/Fail Macros */
/*--------------------------------------------------------------------------------*/
/**
* Increment the number of passed tests in #JTEST_FW.
*/
#define JTEST_FW_INC_PASSED(amount) \
JTEST_PF_INC_PASSED(&JTEST_FW, amount)
/**
* Increment the number of passed tests in #JTEST_FW.
*/
#define JTEST_FW_INC_FAILED(amount) \
JTEST_PF_INC_FAILED(&JTEST_FW, amount)
/* Manipulating the Current Group */
/*--------------------------------------------------------------------------------*/
/**
* Evaluate to the current_group_ptr in #JTEST_FW.
*/
#define JTEST_CURRENT_GROUP_PTR() \
(JTEST_FW.current_group_ptr)
#define JTEST_SET_CURRENT_GROUP(group_ptr) \
do \
{ \
JTEST_CURRENT_GROUP_PTR() = group_ptr; \
} while (0)
/*--------------------------------------------------------------------------------*/
/* Declare Global Variables */
/*--------------------------------------------------------------------------------*/
extern char JTEST_FW_STR_BUFFER[JTEST_BUF_SIZE];
extern volatile JTEST_FW_t JTEST_FW;
/*--------------------------------------------------------------------------------*/
/* Function Prototypes */
/*--------------------------------------------------------------------------------*/
void jtest_dump_str_segments(void);
void test_start (void);
void test_end (void);
void group_start (void);
void group_end (void);
void dump_str (void);
void dump_data (void);
void exit_fw (void);
#endif /* _JTEST_FW_H_ */
@@ -1,66 +0,0 @@
#ifndef _JTEST_GROUP_H_
#define _JTEST_GROUP_H_
/*--------------------------------------------------------------------------------*/
/* Includes */
/*--------------------------------------------------------------------------------*/
#include "jtest_pf.h"
#include "jtest_util.h"
/*--------------------------------------------------------------------------------*/
/* Type Definitions */
/*--------------------------------------------------------------------------------*/
/**
* A struct which represents a group of #JTEST_TEST_t structs. This struct is
* used to run the group of tests, and report on their outcomes.
*/
typedef struct JTEST_GROUP_struct
{
void (* group_fn_ptr) (void); /**< Pointer to the test group */
char * name_str; /**< Name of the group */
/* Extend the #JTEST_GROUP_t with Pass/Fail information.*/
JTEST_PF_MEMBERS;
} JTEST_GROUP_t;
/*--------------------------------------------------------------------------------*/
/* Macros and Defines */
/*--------------------------------------------------------------------------------*/
/**
* Set the name of JTEST_GROUP_t.
*/
#define JTEST_GROUP_SET_NAME(group_ptr, name) \
JTEST_SET_STRUCT_ATTRIBUTE(group_ptr, name_str, name)
#define JTEST_GROUP_SET_FN(group_ptr, fn_ptr) \
JTEST_SET_STRUCT_ATTRIBUTE(group_ptr, group_fn_ptr, fn_ptr)
/**
* Increment the number of tests passed in the JTEST_GROUP_t pointed to by
* group_ptr.
*/
#define JTEST_GROUP_INC_PASSED(group_ptr, amount) \
JTEST_PF_INC_PASSED(group_ptr, amount)
/**
* Increment the number of tests failed in the JTEST_GROUP_t pointed to by
* group_ptr.
*/
#define JTEST_GROUP_INC_FAILED(group_ptr, amount) \
JTEST_PF_INC_FAILED(group_ptr, amount)
/**
* Reset the pass/fail information of the #JTEST_GROUP_t pointed to by
* group_ptr.
*/
#define JTEST_GROUP_RESET_PF(group_ptr) \
do \
{ \
JTEST_PF_RESET_PASSED(group_ptr); \
JTEST_PF_RESET_FAILED(group_ptr); \
} while (0)
#endif /* _JTEST_GROUP_H_ */
@@ -1,126 +0,0 @@
#ifndef _JTEST_GROUP_CALL_H_
#define _JTEST_GROUP_CALL_H_
/*--------------------------------------------------------------------------------*/
/* Includes */
/*--------------------------------------------------------------------------------*/
#include "jtest_fw.h"
#include <inttypes.h>
/*--------------------------------------------------------------------------------*/
/* Macros and Defines */
/*--------------------------------------------------------------------------------*/
/**
* Execute the test in the #JTEST_GROUP_t struct associated witht he identifier
* group_fn.
*/
#define JTEST_GROUP_RUN(group_fn) \
do \
{ \
JTEST_DUMP_STR("Group Name:\n"); \
JTEST_DUMP_STR(JTEST_GROUP_STRUCT_NAME(group_fn).name_str); \
JTEST_GROUP_STRUCT_NAME(group_fn).group_fn_ptr(); \
} while (0)
/**
* Update the enclosing #JTEST_GROUP_t's pass/fail information using the
* current #JTEST_GROUP_t's.
*
* @param group_ptr Pointer to the current #JTEST_GROUP_t.
* @param parent_ptr Pointer to the enclosing #JTEST_GROUP_t.
*
* @warning Only run this if the current #JTEST_GROUP_t is being called within
* the context of another #JTEST_GROUP_t.
*/
#define JTEST_GROUP_UPDATE_PARENT_GROUP_PF(group_ptr, parent_group_ptr) \
do \
{ \
JTEST_GROUP_INC_PASSED(parent_group_ptr, \
(group_ptr)->passed); \
JTEST_GROUP_INC_FAILED(parent_group_ptr, \
(group_ptr)->failed); \
} while (0)
/**
* Update the #JTEST_FW's pass/fail information using the current
* #JTEST_GROUP_t's.
*/
#define JTEST_GROUP_UPDATE_FW_PF(group_ptr) \
do \
{ \
JTEST_FW_INC_PASSED((group_ptr)->passed); \
JTEST_FW_INC_FAILED((group_ptr)->failed); \
} while (0)
/**
* Update the enclosing context with the current #JTEST_GROUP_t's pass/fail
* information. If this group isn't in an enclosing group, it updates the
* #JTEST_FW's pass/fail info by default.
*/
#define JTEST_GROUP_UPDATE_PARENT_GROUP_OR_FW_PF(group_ptr, \
parent_group_ptr) \
do \
{ \
/* Update the pass fail counts in the parent group */ \
if (parent_group_ptr /* Null implies Top*/) \
{ \
JTEST_GROUP_UPDATE_PARENT_GROUP_PF( \
group_ptr, \
parent_group_ptr); \
} else { \
JTEST_GROUP_UPDATE_FW_PF( \
group_ptr); \
} \
} while (0)
/**
* Dump the results of running the #JTEST_GROUP_t to the Keil Debugger.
*/
#define JTEST_GROUP_DUMP_RESULTS(group_ptr) \
do \
{ \
JTEST_DUMP_STRF( \
"Tests Run: %" PRIu32 "\n" \
"----------\n" \
" Passed: %" PRIu32 "\n" \
" Failed: %" PRIu32 "\n", \
(group_ptr)->passed + (group_ptr)->failed, \
(group_ptr)->passed, \
(group_ptr)->failed); \
} while (0)
/**
* Call the #JTEST_GROUP_t associated with the identifier group_fn.
*/
#define JTEST_GROUP_CALL(group_fn) \
do \
{ /* Save the current group from JTEST_FW_t before swapping */ \
/* it to this group (in order to restore it later )*/ \
JTEST_GROUP_t * __jtest_temp_group_ptr = \
JTEST_CURRENT_GROUP_PTR(); \
JTEST_SET_CURRENT_GROUP(&JTEST_GROUP_STRUCT_NAME(group_fn)); \
\
/* Reset this group's pass/fail count. Each group */ \
/* should only remember counts for its last execution. */ \
JTEST_GROUP_RESET_PF(JTEST_CURRENT_GROUP_PTR()); \
\
/* Run the current group */ \
JTEST_ACT_GROUP_START(); \
JTEST_GROUP_RUN(group_fn); \
JTEST_ACT_GROUP_END(); \
\
/* Update the pass fail counts in the parent group (or FW) */ \
JTEST_GROUP_UPDATE_PARENT_GROUP_OR_FW_PF( \
JTEST_CURRENT_GROUP_PTR(), \
__jtest_temp_group_ptr); \
\
JTEST_GROUP_DUMP_RESULTS(JTEST_CURRENT_GROUP_PTR()); \
\
/* Restore the previously current group */ \
JTEST_SET_CURRENT_GROUP(__jtest_temp_group_ptr); \
} while (0)
#endif /* _JTEST_GROUP_CALL_H_ */

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