EPS: update board dimensions

Solar_module_XY
Petr Malanik 3 years ago
parent 4797b96ddd
commit e57654efa0

@ -3,3 +3,4 @@ EPS_V5/
Hierarchy_test/
Replicate_test/
replicate_layout.log
bom/

File diff suppressed because it is too large Load Diff

@ -37,7 +37,6 @@
8,
9,
10,
11,
12,
13,
14,
@ -64,7 +63,7 @@
36
],
"visible_layers": "ffcffff_ffffffff",
"zone_display_mode": 0
"zone_display_mode": 1
},
"meta": {
"filename": "EPS.kicad_prl",

@ -48,7 +48,13 @@
"min_clearance": 0.508
}
},
"diff_pair_dimensions": [],
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"version": 2
@ -110,8 +116,15 @@
"solder_mask_min_width": 0.0,
"use_height_for_length_calcs": true
},
"track_widths": [],
"via_dimensions": [],
"track_widths": [
0.0
],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
}
],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
@ -338,7 +351,7 @@
"classes": [
{
"bus_width": 6.0,
"clearance": 0.2,
"clearance": 0.15,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
@ -348,7 +361,7 @@
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"track_width": 0.15,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0

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