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EPS: connector placement, activation logic routing

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This commit is contained in:
Petr Malanik
2021-08-26 22:00:31 +02:00
parent effacaff11
commit 8e342d1234
3 changed files with 54387 additions and 10582 deletions
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64954
modules/EPS/EPS.kicad_pcb
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File diff suppressed because it is too large Load Diff

7
modules/EPS/EPS.kicad_prl
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@ -1,8 +1,8 @@
{ {
"board": { "board": {
"active_layer": 0, "active_layer": 31,
"active_layer_preset": "", "active_layer_preset": "",
"auto_track_width": true, "auto_track_width": false,
"hidden_nets": [], "hidden_nets": [],
"high_contrast_mode": 0, "high_contrast_mode": 0,
"net_color_mode": 1, "net_color_mode": 1,
@ -37,6 +37,7 @@
8, 8,
9, 9,
10, 10,
11,
12, 12,
13, 13,
14, 14,
@ -63,7 +64,7 @@
36 36
], ],
"visible_layers": "7fcffff_80000007", "visible_layers": "7fcffff_80000007",
"zone_display_mode": 1 "zone_display_mode": 0
}, },
"meta": { "meta": {
"filename": "EPS.kicad_prl", "filename": "EPS.kicad_prl",

8
modules/EPS/EPS.kicad_pro
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@ -33,9 +33,9 @@
"other_text_thickness": 0.15, "other_text_thickness": 0.15,
"other_text_upright": false, "other_text_upright": false,
"pads": { "pads": {
"drill": 0.762, "drill": 2.0,
"height": 1.524, "height": 4.0,
"width": 1.524 "width": 4.0
}, },
"silk_line_width": 0.15, "silk_line_width": 0.15,
"silk_text_italic": false, "silk_text_italic": false,
@ -45,7 +45,7 @@
"silk_text_upright": false, "silk_text_upright": false,
"zones": { "zones": {
"45_degree_only": false, "45_degree_only": false,
"min_clearance": 0.508 "min_clearance": 0.19999999999999998
} }
}, },
"diff_pair_dimensions": [ "diff_pair_dimensions": [