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Solar_module_XY: add capacitors and address resistors to ADC

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This commit is contained in:
Petr Malanik
2021-06-03 13:33:43 +02:00
parent 11f9d3780a
commit 45f6e4e50c
5 changed files with 392 additions and 110 deletions
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40
Solar_module_XY/Solar_module_XY.kicad_pro
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@ -39,13 +39,13 @@
},
"silk_line_width": 0.15,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_size_h": 0.7,
"silk_text_size_v": 0.7,
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.0
"min_clearance": 0.19999999999999998
}
},
"diff_pair_dimensions": [
@ -101,24 +101,24 @@
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_copper_edge_clearance": 0.0,
"min_hole_clearance": 0.0,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_clearance": 0.15,
"min_copper_edge_clearance": 0.19999999999999998,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.44999999999999996,
"min_microvia_diameter": 0.6,
"min_microvia_drill": 0.3,
"min_silk_clearance": 0.0,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.19999999999999998,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.39999999999999997,
"min_track_width": 0.15,
"min_via_annular_width": 0.15,
"min_via_diameter": 0.6,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0,
"use_height_for_length_calcs": true
},
"track_widths": [
0.0,
0.127,
0.15,
0.25,
0.5,
1.0
@ -354,19 +354,19 @@
"classes": [
{
"bus_width": 6.0,
"clearance": 0.2,
"clearance": 0.15,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"microvia_diameter": 0.6,
"microvia_drill": 0.3,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"track_width": 0.15,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6.0
}
],
@ -381,7 +381,7 @@
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"step": "Solar_module_XY.step",
"vrml": ""
},
"page_layout_descr_file": ""