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ProfilometerProbe
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Auto config, no need to init before each capture, 320x240 cca 5fps

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Adam Prochazka 2 years ago
parent 374a63bc0c
commit 58b09c93ab
4 changed files with 752 additions and 908 deletions
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38
Firmware/Core/Cam/Cam.c
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@ -120,27 +120,37 @@ void Cam_I2C_write_bulk(I2C_HandleTypeDef *hi2c, const struct sensor_reg regList
void Cam_Init(I2C_HandleTypeDef *hi2c, SPI_HandleTypeDef *hspi) void Cam_Init(I2C_HandleTypeDef *hi2c, SPI_HandleTypeDef *hspi)
{ {
Cam_I2C_write(hi2c, (uint16_t)0x3008, 0x80); Cam_SPI_write(hspi, 0x07, 0x80);
HAL_Delay(100);
Cam_SPI_write(hspi, 0x07, 0x00);
HAL_Delay(100);
//Cam_SPI_write(hspi, 0x00, 0x55);
HAL_Delay(5);
Cam_I2C_write(hi2c, (uint16_t)0x3008, 0x80);
HAL_Delay(5);
Cam_I2C_write_bulk(hi2c, OV5642_QVGA_Preview); Cam_I2C_write_bulk(hi2c, OV5642_QVGA_Preview);
HAL_Delay(200);
Cam_I2C_write_bulk(hi2c, OV5642_JPEG_Capture_QSXGA); Cam_I2C_write_bulk(hi2c, OV5642_JPEG_Capture_QSXGA);
Cam_I2C_write_bulk(hi2c, ov5642_320x240);
HAL_Delay(100);
//Cam_I2C_write_bulk(hi2c, OV5642_720P_Video_setting); //Cam_I2C_write_bulk(hi2c, OV5642_720P_Video_setting);
Cam_I2C_write(hi2c, (uint16_t)0x3818, 0xa8); // TIMING CONTROL - ENABLE COMPRESSION, THUMBNAIL MODE DISABLE, VERTICAL FLIP, MIRROR Cam_I2C_write(hi2c, (uint16_t)0x3818, 0xa8); // TIMING CONTROL - ENABLE COMPRESSION, THUMBNAIL MODE DISABLE, VERTICAL FLIP, MIRROR
Cam_I2C_write(hi2c, (uint16_t)0x3621, 0x10); // REGISTER FOR CORRECT MIRROR FUNCTION Cam_I2C_write(hi2c, (uint16_t)0x3621, 0x10); // REGISTER FOR CORRECT MIRROR FUNCTION
Cam_I2C_write(hi2c, (uint16_t)0x3801, 0xb0); // TIMING HORIZONTAL START - ALSO FOR MIRROR Cam_I2C_write(hi2c, (uint16_t)0x3801, 0xb0); // TIMING HORIZONTAL START - ALSO FOR MIRROR
Cam_I2C_write(hi2c, (uint16_t)0x4407, 0x04); // COMPRESSION CONTROL Cam_I2C_write(hi2c, (uint16_t)0x4407, 0x04); // COMPRESSION CONTROL
Cam_I2C_write(hi2c, (uint16_t)0x5000, 0xFF); //Cam_I2C_write(hi2c, (uint16_t)0x5000, 0xFF);
HAL_Delay(5);
Cam_I2C_write_bulk(hi2c, ov5642_1024x768);
// Setup camera, H-sync: High, V-sync:high, Sensor_delay: no Delay, FIFO_mode:FIFO enabled, power_mode:Low_power // Setup camera, H-sync: High, V-sync:high, Sensor_delay: no Delay, FIFO_mode:FIFO enabled, power_mode:Low_power
Cam_SPI_write(hspi, 0x03, 0x02); Cam_SPI_write(hspi, 0x03, 0x02);
HAL_Delay(5);
//Cam_I2C_write_bulk(hi2c, ov5642_1024x768);
Cam_I2C_write_bulk(hi2c, ov5642_320x240);
HAL_Delay(1000);
Cam_SPI_write(hspi, 0x04, 0x01);
HAL_Delay(5);
Cam_SPI_write(hspi, 0x01, 0x00); // Capture Control Register - Set to capture n+1 frames Cam_SPI_write(hspi, 0x01, 0x00); // Capture Control Register - Set to capture n+1 frames
HAL_Delay(5); HAL_Delay(5);
/* /*
Cam_I2C_write(hi2c, (uint16_t)0x3008, 0x80); Cam_I2C_write(hi2c, (uint16_t)0x3008, 0x80);
@ -275,9 +285,8 @@ void Cam_Refresh(I2C_HandleTypeDef *hi2c, SPI_HandleTypeDef *hspi){
Cam_I2C_write(hi2c, (uint16_t)0x3404, 0xf); Cam_I2C_write(hi2c, (uint16_t)0x3404, 0xf);
Cam_I2C_write(hi2c, (uint16_t)0x3405, 0xff); Cam_I2C_write(hi2c, (uint16_t)0x3405, 0xff);
Cam_SPI_write(hspi, 0x01, 0x00); // Capture Control Register - Set to capture n+1 frames
HAL_Delay(5); HAL_Delay(50);
} }
int Cam_FIFO_length(SPI_HandleTypeDef *hspi) int Cam_FIFO_length(SPI_HandleTypeDef *hspi)
@ -311,11 +320,12 @@ void Cam_Start_Capture(SPI_HandleTypeDef *hspi)
Cam_SPI_write(hspi, 0x04, FIFO_Reg_Clear_Flags); Cam_SPI_write(hspi, 0x04, FIFO_Reg_Clear_Flags);
*/ */
Cam_SPI_write(hspi, 0x04, 0x01); Cam_SPI_write(hspi, 0x04, 0x01);
HAL_Delay(3);
Cam_SPI_write(hspi, 0x04, 0x01); Cam_SPI_write(hspi, 0x04, 0x01);
HAL_Delay(10); HAL_Delay(3);
Cam_SPI_write(hspi, 0x04, 0x02); // Start capture Cam_SPI_write(hspi, 0x04, 0x02); // Start capture
HAL_Delay(10); HAL_Delay(3);
} }
void Cam_Wait_Capture_Done(SPI_HandleTypeDef *hspi) void Cam_Wait_Capture_Done(SPI_HandleTypeDef *hspi)
@ -354,6 +364,8 @@ void Cam_Capture(SPI_HandleTypeDef *hspi)
{ {
//LED_On(); //LED_On();
Cam_SPI_write(hspi, 0x01, 0x00); // Capture Control Register - Set to capture n+1 frames
Cam_Start_Capture(hspi); Cam_Start_Capture(hspi);
Cam_Wait_Capture_Done(hspi); Cam_Wait_Capture_Done(hspi);

1466
Firmware/Core/Cam/OV5642_regs.h
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File diff suppressed because it is too large Load Diff

2
Firmware/Core/Inc/main.h
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@ -86,7 +86,7 @@ void Error_Handler(void);
#define LD3_GPIO_Port GPIOB #define LD3_GPIO_Port GPIOB
/* USER CODE BEGIN Private defines */ /* USER CODE BEGIN Private defines */
#define CDC_BUFF_SIZE 10048 #define CDC_BUFF_SIZE 12800
#define CDC_FRAME_SIZE 64 #define CDC_FRAME_SIZE 64
#define CDC_FRAME_DELAY 1 #define CDC_FRAME_DELAY 1
/* USER CODE END Private defines */ /* USER CODE END Private defines */

162
Firmware/Core/Src/main.c
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@ -73,151 +73,7 @@ static void MX_USB_PCD_Init(void);
/* Private user code ---------------------------------------------------------*/ /* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */ /* USER CODE BEGIN 0 */
/*
static unsigned frame_num = 0;
static unsigned tx_busy = 0;
static unsigned interval_ms = 1000 / FRAME_RATE;
static struct {
uint32_t size;
uint8_t const *buffer;
} const frames[] = {
{color_bar_0_jpg_len, color_bar_0_jpg},
{color_bar_1_jpg_len, color_bar_1_jpg},
{color_bar_2_jpg_len, color_bar_2_jpg},
{color_bar_3_jpg_len, color_bar_3_jpg},
{color_bar_4_jpg_len, color_bar_4_jpg},
{color_bar_5_jpg_len, color_bar_5_jpg},
{color_bar_6_jpg_len, color_bar_6_jpg},
{color_bar_7_jpg_len, color_bar_7_jpg},
};
*/
/*
void cdc_task(void)
{
// connected() check for DTR bit
// Most but not all terminal client set this when making connection
// if ( tud_cdc_connected() )
{
// connected and there are data available
if (tud_cdc_available())
{
// read data
char buf[64];
uint32_t count = tud_cdc_read(buf, sizeof(buf));
(void)count;
//char buf_2[10] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9'};
//uint32_t count_2 = 10;
// Echo back
// Note: Skip echo by commenting out write() and write_flush()
// for throughput test e.g
// $ dd if=/dev/zero of=/dev/ttyACM0 count=10000
tud_cdc_write(buf, count);
//tud_cdc_n_write(10, buf_2, count_2);
tud_cdc_write_flush();
}
}
}
*/
uint8_t sendT[700] = {
0xff, 0xd8, 0xff, 0xdb, 0x00, 0x43, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdb, 0x00, 0x43, 0x01, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x00, 0x11,
0x08, 0x00, 0x60, 0x00, 0x80, 0x03, 0x01, 0x21, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11, 0x01, 0xff,
0xda, 0x00, 0x0c, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11, 0x00, 0x3f, 0x00, 0x92, 0x8a, 0x00,
0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45,
0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89,
0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad,
0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25,
0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3,
0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1,
0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00,
0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45,
0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89,
0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad,
0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25,
0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3,
0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1,
0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00,
0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45,
0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89,
0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad,
0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25,
0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3,
0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1,
0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0xff, 0xd9, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
/*
int currentIdx = 0;
int currentImg = 0;
int send_CDC_Bulk(){
if(currentIdx + 10 > 530){
currentIdx = 0;
currentImg++;
currentImg %=8;
}
switch(currentImg){
case 0:
tud_cdc_write(&color_bar_0_jpg[currentIdx], 10);
break;
case 1:
tud_cdc_write(&color_bar_1_jpg[currentIdx], 10);
break;
case 2:
tud_cdc_write(&color_bar_2_jpg[currentIdx], 10);
break;
case 3:
tud_cdc_write(&color_bar_3_jpg[currentIdx], 10);
break;
case 4:
tud_cdc_write(&color_bar_4_jpg[currentIdx], 10);
break;
case 5:
tud_cdc_write(&color_bar_5_jpg[currentIdx], 10);
break;
case 6:
tud_cdc_write(&color_bar_6_jpg[currentIdx], 10);
break;
case 7:
tud_cdc_write(&color_bar_7_jpg[currentIdx], 10);
break;
default:
break;
}
//tud_cdc_write(&sendT[currentIdx], 10);
tud_cdc_write_flush();
currentIdx = currentIdx + 10;
return 1;
}
*/
void SysTick_Init(void) void SysTick_Init(void)
{ {
SysTick_Config(SystemCoreClock / 10000); // Set SysTick interrupt to occur every 100us SysTick_Config(SystemCoreClock / 10000); // Set SysTick interrupt to occur every 100us
@ -311,7 +167,8 @@ int main(void)
tud_task(); tud_task();
Cam_Refresh(&hi2c1, &hspi1); //Cam_Refresh(&hi2c1, &hspi1);
//Cam_Init(&hi2c1, &hspi1);
tud_task(); tud_task();
@ -326,7 +183,6 @@ int main(void)
continue; continue;
//HAL_SPI_Receive(&hspi1, cdc_buff, CDC_BUFF_SIZE, HAL_MAX_DELAY);
} }
else { else {
int number_to_read = 0; int number_to_read = 0;
@ -346,13 +202,19 @@ int main(void)
int current_sending_idx = 0; int current_sending_idx = 0;
do{ do{
tud_task(); tud_task();
tud_cdc_write(&cdc_buff[current_sending_idx], CDC_FRAME_SIZE); int sendLen = CDC_FRAME_SIZE;
current_sending_idx = current_sending_idx + CDC_FRAME_SIZE; if(last_sent_idx + CDC_FRAME_SIZE > buff_stop_idx){
last_sent_idx = last_sent_idx + CDC_FRAME_SIZE; sendLen = buff_stop_idx - last_sent_idx;
}
tud_cdc_write(&cdc_buff[current_sending_idx], sendLen);
current_sending_idx = current_sending_idx + sendLen;
last_sent_idx = last_sent_idx + sendLen;
tud_cdc_write_flush(); tud_cdc_write_flush();
//Delay between sends //Delay between sends
int i = 0; int i = 0;
for(;i<4000;i++); for(;i<7000;i++);
} }
while(last_sent_idx < buff_stop_idx); while(last_sent_idx < buff_stop_idx);

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