mirror of
https://github.com/aprochazka/ProfilometerProbe.git
synced 2025-06-30 01:27:23 +02:00
Auto config, no need to init before each capture, 320x240 cca 5fps
This commit is contained in:
Adam Prochazka
@ -120,27 +120,37 @@ void Cam_I2C_write_bulk(I2C_HandleTypeDef *hi2c, const struct sensor_reg regList
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void Cam_Init(I2C_HandleTypeDef *hi2c, SPI_HandleTypeDef *hspi)
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{
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Cam_SPI_write(hspi, 0x07, 0x80);
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HAL_Delay(100);
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Cam_SPI_write(hspi, 0x07, 0x00);
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HAL_Delay(100);
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//Cam_SPI_write(hspi, 0x00, 0x55);
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HAL_Delay(5);
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Cam_I2C_write(hi2c, (uint16_t)0x3008, 0x80);
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HAL_Delay(5);
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Cam_I2C_write_bulk(hi2c, OV5642_QVGA_Preview);
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HAL_Delay(200);
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Cam_I2C_write_bulk(hi2c, OV5642_JPEG_Capture_QSXGA);
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Cam_I2C_write_bulk(hi2c, ov5642_320x240);
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HAL_Delay(100);
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//Cam_I2C_write_bulk(hi2c, OV5642_720P_Video_setting);
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Cam_I2C_write(hi2c, (uint16_t)0x3818, 0xa8); // TIMING CONTROL - ENABLE COMPRESSION, THUMBNAIL MODE DISABLE, VERTICAL FLIP, MIRROR
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Cam_I2C_write(hi2c, (uint16_t)0x3621, 0x10); // REGISTER FOR CORRECT MIRROR FUNCTION
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Cam_I2C_write(hi2c, (uint16_t)0x3801, 0xb0); // TIMING HORIZONTAL START - ALSO FOR MIRROR
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Cam_I2C_write(hi2c, (uint16_t)0x4407, 0x04); // COMPRESSION CONTROL
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Cam_I2C_write(hi2c, (uint16_t)0x5000, 0xFF);
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Cam_I2C_write_bulk(hi2c, ov5642_1024x768);
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//Cam_I2C_write(hi2c, (uint16_t)0x5000, 0xFF);
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HAL_Delay(5);
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// Setup camera, H-sync: High, V-sync:high, Sensor_delay: no Delay, FIFO_mode:FIFO enabled, power_mode:Low_power
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Cam_SPI_write(hspi, 0x03, 0x02);
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HAL_Delay(5);
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//Cam_I2C_write_bulk(hi2c, ov5642_1024x768);
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Cam_I2C_write_bulk(hi2c, ov5642_320x240);
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HAL_Delay(1000);
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Cam_SPI_write(hspi, 0x04, 0x01);
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HAL_Delay(5);
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Cam_SPI_write(hspi, 0x01, 0x00); // Capture Control Register - Set to capture n+1 frames
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HAL_Delay(5);
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/*
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Cam_I2C_write(hi2c, (uint16_t)0x3008, 0x80);
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@ -275,9 +285,8 @@ void Cam_Refresh(I2C_HandleTypeDef *hi2c, SPI_HandleTypeDef *hspi){
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Cam_I2C_write(hi2c, (uint16_t)0x3404, 0xf);
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Cam_I2C_write(hi2c, (uint16_t)0x3405, 0xff);
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Cam_SPI_write(hspi, 0x01, 0x00); // Capture Control Register - Set to capture n+1 frames
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HAL_Delay(5);
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HAL_Delay(50);
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}
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int Cam_FIFO_length(SPI_HandleTypeDef *hspi)
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@ -311,11 +320,12 @@ void Cam_Start_Capture(SPI_HandleTypeDef *hspi)
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Cam_SPI_write(hspi, 0x04, FIFO_Reg_Clear_Flags);
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*/
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Cam_SPI_write(hspi, 0x04, 0x01);
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HAL_Delay(3);
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Cam_SPI_write(hspi, 0x04, 0x01);
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HAL_Delay(10);
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HAL_Delay(3);
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Cam_SPI_write(hspi, 0x04, 0x02); // Start capture
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HAL_Delay(10);
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HAL_Delay(3);
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}
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void Cam_Wait_Capture_Done(SPI_HandleTypeDef *hspi)
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@ -354,6 +364,8 @@ void Cam_Capture(SPI_HandleTypeDef *hspi)
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{
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//LED_On();
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Cam_SPI_write(hspi, 0x01, 0x00); // Capture Control Register - Set to capture n+1 frames
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Cam_Start_Capture(hspi);
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Cam_Wait_Capture_Done(hspi);
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File diff suppressed because it is too large
Load Diff
@ -86,7 +86,7 @@ void Error_Handler(void);
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#define LD3_GPIO_Port GPIOB
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/* USER CODE BEGIN Private defines */
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#define CDC_BUFF_SIZE 10048
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#define CDC_BUFF_SIZE 12800
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#define CDC_FRAME_SIZE 64
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#define CDC_FRAME_DELAY 1
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/* USER CODE END Private defines */
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@ -73,151 +73,7 @@ static void MX_USB_PCD_Init(void);
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/* Private user code ---------------------------------------------------------*/
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/* USER CODE BEGIN 0 */
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/*
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static unsigned frame_num = 0;
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static unsigned tx_busy = 0;
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static unsigned interval_ms = 1000 / FRAME_RATE;
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static struct {
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uint32_t size;
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uint8_t const *buffer;
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} const frames[] = {
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{color_bar_0_jpg_len, color_bar_0_jpg},
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{color_bar_1_jpg_len, color_bar_1_jpg},
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{color_bar_2_jpg_len, color_bar_2_jpg},
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{color_bar_3_jpg_len, color_bar_3_jpg},
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{color_bar_4_jpg_len, color_bar_4_jpg},
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{color_bar_5_jpg_len, color_bar_5_jpg},
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{color_bar_6_jpg_len, color_bar_6_jpg},
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{color_bar_7_jpg_len, color_bar_7_jpg},
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};
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*/
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/*
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void cdc_task(void)
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{
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// connected() check for DTR bit
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// Most but not all terminal client set this when making connection
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// if ( tud_cdc_connected() )
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{
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// connected and there are data available
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if (tud_cdc_available())
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{
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// read data
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char buf[64];
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uint32_t count = tud_cdc_read(buf, sizeof(buf));
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(void)count;
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//char buf_2[10] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9'};
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//uint32_t count_2 = 10;
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// Echo back
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// Note: Skip echo by commenting out write() and write_flush()
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// for throughput test e.g
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// $ dd if=/dev/zero of=/dev/ttyACM0 count=10000
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tud_cdc_write(buf, count);
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//tud_cdc_n_write(10, buf_2, count_2);
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tud_cdc_write_flush();
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}
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}
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}
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*/
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uint8_t sendT[700] = {
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0xff, 0xd8, 0xff, 0xdb, 0x00, 0x43, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdb, 0x00, 0x43, 0x01, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x00, 0x11,
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0x08, 0x00, 0x60, 0x00, 0x80, 0x03, 0x01, 0x21, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11, 0x01, 0xff,
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0xda, 0x00, 0x0c, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11, 0x00, 0x3f, 0x00, 0x92, 0x8a, 0x00,
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0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45,
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0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89,
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0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad,
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0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25,
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0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3,
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0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1,
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0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00,
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0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45,
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0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89,
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0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad,
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0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25,
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0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3,
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0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1,
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0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00,
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0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45,
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0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89,
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0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad,
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0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25,
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0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3,
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0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1,
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0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0xff, 0xd9, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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};
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/*
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int currentIdx = 0;
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int currentImg = 0;
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int send_CDC_Bulk(){
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if(currentIdx + 10 > 530){
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currentIdx = 0;
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currentImg++;
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currentImg %=8;
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}
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switch(currentImg){
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case 0:
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tud_cdc_write(&color_bar_0_jpg[currentIdx], 10);
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break;
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case 1:
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tud_cdc_write(&color_bar_1_jpg[currentIdx], 10);
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break;
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case 2:
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tud_cdc_write(&color_bar_2_jpg[currentIdx], 10);
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break;
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case 3:
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tud_cdc_write(&color_bar_3_jpg[currentIdx], 10);
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break;
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case 4:
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tud_cdc_write(&color_bar_4_jpg[currentIdx], 10);
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break;
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case 5:
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tud_cdc_write(&color_bar_5_jpg[currentIdx], 10);
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break;
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case 6:
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tud_cdc_write(&color_bar_6_jpg[currentIdx], 10);
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break;
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case 7:
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tud_cdc_write(&color_bar_7_jpg[currentIdx], 10);
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break;
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default:
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break;
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}
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//tud_cdc_write(&sendT[currentIdx], 10);
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tud_cdc_write_flush();
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currentIdx = currentIdx + 10;
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return 1;
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}
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*/
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void SysTick_Init(void)
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{
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SysTick_Config(SystemCoreClock / 10000); // Set SysTick interrupt to occur every 100us
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@ -311,8 +167,9 @@ int main(void)
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tud_task();
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Cam_Refresh(&hi2c1, &hspi1);
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//Cam_Refresh(&hi2c1, &hspi1);
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//Cam_Init(&hi2c1, &hspi1);
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tud_task();
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Cam_Capture(&hspi1);
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@ -326,7 +183,6 @@ int main(void)
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continue;
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//HAL_SPI_Receive(&hspi1, cdc_buff, CDC_BUFF_SIZE, HAL_MAX_DELAY);
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}
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else {
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int number_to_read = 0;
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@ -346,13 +202,19 @@ int main(void)
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int current_sending_idx = 0;
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do{
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tud_task();
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tud_cdc_write(&cdc_buff[current_sending_idx], CDC_FRAME_SIZE);
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current_sending_idx = current_sending_idx + CDC_FRAME_SIZE;
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last_sent_idx = last_sent_idx + CDC_FRAME_SIZE;
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int sendLen = CDC_FRAME_SIZE;
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if(last_sent_idx + CDC_FRAME_SIZE > buff_stop_idx){
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sendLen = buff_stop_idx - last_sent_idx;
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}
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tud_cdc_write(&cdc_buff[current_sending_idx], sendLen);
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current_sending_idx = current_sending_idx + sendLen;
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last_sent_idx = last_sent_idx + sendLen;
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tud_cdc_write_flush();
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//Delay between sends
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int i = 0;
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for(;i<4000;i++);
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for(;i<7000;i++);
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}
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while(last_sent_idx < buff_stop_idx);
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