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@ -121,11 +121,13 @@ void Cam_I2C_write_bulk(I2C_HandleTypeDef *hi2c, const struct sensor_reg regList
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void Cam_Init(I2C_HandleTypeDef *hi2c, SPI_HandleTypeDef *hspi)
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void Cam_Init(I2C_HandleTypeDef *hi2c, SPI_HandleTypeDef *hspi)
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{
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{
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Cam_I2C_write(hi2c, (uint16_t)0x3008, 0x80);
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Cam_I2C_write(hi2c, (uint16_t)0x3008, 0x80);
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Cam_I2C_write(hi2c, (uint16_t)0x3008, 0x80);
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Cam_I2C_write_bulk(hi2c, OV5642_QVGA_Preview);
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// Cam_I2C_write_bulk(hi2c, OV5642_QVGA_Preview);
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Cam_I2C_write_bulk(hi2c, OV5642_JPEG_Capture_QSXGA);
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Cam_I2C_write_bulk(hi2c, OV5642_JPEG_Capture_QSXGA);
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// am_I2C_write_bulk(hi2c, OV5642_720P_Video_setting);
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Cam_I2C_write_bulk(hi2c, OV5642_720P_Video_setting);
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Cam_I2C_write(hi2c, (uint16_t)0x3818, 0xa8); // TIMING CONTROL - ENABLE COMPRESSION, THUMBNAIL MODE DISABLE, VERTICAL FLIP, MIRROR
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Cam_I2C_write(hi2c, (uint16_t)0x3818, 0xa8); // TIMING CONTROL - ENABLE COMPRESSION, THUMBNAIL MODE DISABLE, VERTICAL FLIP, MIRROR
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Cam_I2C_write(hi2c, (uint16_t)0x3621, 0x10); // REGISTER FOR CORRECT MIRROR FUNCTION
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Cam_I2C_write(hi2c, (uint16_t)0x3621, 0x10); // REGISTER FOR CORRECT MIRROR FUNCTION
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@ -136,7 +138,9 @@ void Cam_Init(I2C_HandleTypeDef *hi2c, SPI_HandleTypeDef *hspi)
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// Setup camera, H-sync: High, V-sync:high, Sensor_delay: no Delay, FIFO_mode:FIFO enabled, power_mode:Low_power
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// Setup camera, H-sync: High, V-sync:high, Sensor_delay: no Delay, FIFO_mode:FIFO enabled, power_mode:Low_power
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Cam_SPI_write(hspi, 0x03, 0x02);
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Cam_SPI_write(hspi, 0x03, 0x02);
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Cam_SPI_write(hspi, 0x01, 0x00); // Capture Control Register - Set to capture n+1 frames
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Cam_SPI_write(hspi, 0x01, 0x01); // Capture Control Register - Set to capture n+1 frames
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HAL_Delay(5);
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}
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}
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int Cam_FIFO_length(SPI_HandleTypeDef *hspi)
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int Cam_FIFO_length(SPI_HandleTypeDef *hspi)
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@ -187,11 +191,17 @@ void Cam_Wait_Capture_Done(SPI_HandleTypeDef *hspi)
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void Cam_Start_Burst_Read(SPI_HandleTypeDef *hspi)
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void Cam_Start_Burst_Read(SPI_HandleTypeDef *hspi)
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{
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{
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CS_On();
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uint8_t FIFO_Reg = Cam_SPI_read(hspi, 0x04);
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uint8_t FIFO_Reg_Clear_Flags = FIFO_Reg | 0x20;
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Cam_SPI_write(hspi, 0x04, FIFO_Reg_Clear_Flags); // Reset FIFO Read Pointer
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Cam_SPI_write(hspi, 0x04, FIFO_Reg_Clear_Flags);
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uint8_t BURST_FIFO_READ = 0x3c;
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uint8_t BURST_FIFO_READ = 0x3c;
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uint8_t empty = 0x00;
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uint8_t empty = 0x00;
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CS_On();
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HAL_SPI_TransmitReceive(hspi, &BURST_FIFO_READ, &empty, 1, HAL_MAX_DELAY);
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HAL_SPI_TransmitReceive(hspi, &BURST_FIFO_READ, &empty, 1, HAL_MAX_DELAY);
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}
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}
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